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{ "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "name": "arm: Implement an emulation of GICv5 interrupt controller", "date": "2026-03-27T11:16:25", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "version": 2, "total": 65, "received_total": 64, "received_all": false, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/", "cover_letter": { "id": 2216871, "url": "http://patchwork.ozlabs.org/api/covers/2216871/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260327111700.795099-1-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-1-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:15:55", "name": "[v2,00/65] arm: Implement an emulation of GICv5 interrupt controller", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260327111700.795099-1-peter.maydell@linaro.org/mbox/" }, "patches": [ { "id": 2216879, "url": "http://patchwork.ozlabs.org/api/patches/2216879/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-2-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-2-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:15:56", "name": "[v2,01/65] qom/object: Add object_resolve_and_typecheck()", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-2-peter.maydell@linaro.org/mbox/" }, { "id": 2216911, "url": "http://patchwork.ozlabs.org/api/patches/2216911/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-3-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-3-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:15:57", "name": "[v2,02/65] hw/core: Permit devices to define an array of link properties", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-3-peter.maydell@linaro.org/mbox/" }, { "id": 2216907, "url": "http://patchwork.ozlabs.org/api/patches/2216907/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-4-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-4-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:15:58", "name": "[v2,03/65] hw/intc: Skeleton of GICv5 IRS classes", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-4-peter.maydell@linaro.org/mbox/" }, { "id": 2216908, "url": "http://patchwork.ozlabs.org/api/patches/2216908/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-5-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-5-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:15:59", "name": "[v2,04/65] hw/arm/Kconfig: select ARM_GICV5 for ARM_VIRT board", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-5-peter.maydell@linaro.org/mbox/" }, { "id": 2216918, "url": "http://patchwork.ozlabs.org/api/patches/2216918/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-6-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-6-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:00", "name": "[v2,05/65] hw/intc/arm_gicv5: Implement skeleton code for IRS register frames", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-6-peter.maydell@linaro.org/mbox/" }, { "id": 2216933, "url": "http://patchwork.ozlabs.org/api/patches/2216933/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-8-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-8-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:02", "name": "[v2,07/65] hw/intc/arm_gicv5: Create and validate QOM properties", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-8-peter.maydell@linaro.org/mbox/" }, { "id": 2216924, "url": "http://patchwork.ozlabs.org/api/patches/2216924/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-9-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-9-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:03", "name": "[v2,08/65] hw/intc/arm_gicv5: Create inbound GPIO lines for SPIs", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-9-peter.maydell@linaro.org/mbox/" }, { "id": 2216922, "url": "http://patchwork.ozlabs.org/api/patches/2216922/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-10-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-10-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:04", "name": "[v2,09/65] hw/intc/arm_gicv5: Define macros for config frame registers", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-10-peter.maydell@linaro.org/mbox/" }, { "id": 2216891, "url": "http://patchwork.ozlabs.org/api/patches/2216891/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-11-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-11-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:05", "name": "[v2,10/65] hw/intc/arm_gicv5: Implement IRS ID regs", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-11-peter.maydell@linaro.org/mbox/" }, { "id": 2216901, "url": "http://patchwork.ozlabs.org/api/patches/2216901/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-12-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-12-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:06", "name": "[v2,11/65] hw/intc/arm_gicv5: Add link property for MemoryRegion for DMA", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-12-peter.maydell@linaro.org/mbox/" }, { "id": 2216882, "url": "http://patchwork.ozlabs.org/api/patches/2216882/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-13-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-13-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:07", "name": "[v2,12/65] hw/intc/arm_gicv5: Implement gicv5_class_name()", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-13-peter.maydell@linaro.org/mbox/" }, { "id": 2216885, "url": "http://patchwork.ozlabs.org/api/patches/2216885/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-14-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-14-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:08", "name": "[v2,13/65] hw/intc/arm_gicv5: Add defines for GICv5 architected PPIs", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-14-peter.maydell@linaro.org/mbox/" }, { "id": 2216936, "url": "http://patchwork.ozlabs.org/api/patches/2216936/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-15-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-15-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:09", "name": "[v2,14/65] target/arm: GICv5 cpuif: Initial skeleton and GSB barrier insns", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-15-peter.maydell@linaro.org/mbox/" }, { "id": 2216895, "url": "http://patchwork.ozlabs.org/api/patches/2216895/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-16-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-16-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:10", "name": "[v2,15/65] target/arm: Set up pointer to GICv5 in each CPU", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-16-peter.maydell@linaro.org/mbox/" }, { "id": 2216931, "url": "http://patchwork.ozlabs.org/api/patches/2216931/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-17-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-17-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:11", "name": "[v2,16/65] hw/intc/arm_gicv5: Implement IRS_IST_{BASER, STATUSR, CFGR}", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-17-peter.maydell@linaro.org/mbox/" }, { "id": 2216937, "url": "http://patchwork.ozlabs.org/api/patches/2216937/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-18-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-18-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:12", "name": "[v2,17/65] hw/intc/arm_gicv5: Cache LPI IST config in a struct", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-18-peter.maydell@linaro.org/mbox/" }, { "id": 2216884, "url": "http://patchwork.ozlabs.org/api/patches/2216884/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-19-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-19-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:13", "name": "[v2,18/65] hw/intc/arm_gicv5: Implement gicv5_set_priority()", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-19-peter.maydell@linaro.org/mbox/" }, { "id": 2216898, "url": "http://patchwork.ozlabs.org/api/patches/2216898/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-20-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-20-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:14", "name": "[v2,19/65] target/arm: GICv5 cpuif: Implement the GIC CDPRI instruction", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-20-peter.maydell@linaro.org/mbox/" }, { "id": 2216902, "url": "http://patchwork.ozlabs.org/api/patches/2216902/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-21-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-21-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:15", "name": "[v2,20/65] hw/intc/arm_gicv5: Implement IRS_MAP_L2_ISTR", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-21-peter.maydell@linaro.org/mbox/" }, { "id": 2216921, "url": "http://patchwork.ozlabs.org/api/patches/2216921/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-22-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-22-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:16", "name": "[v2,21/65] hw/intc/arm_gicv5: Implement remaining set-config functions", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-22-peter.maydell@linaro.org/mbox/" }, { "id": 2216932, "url": "http://patchwork.ozlabs.org/api/patches/2216932/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-23-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-23-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:17", "name": "[v2,22/65] target/arm: GICv5 cpuif: Implement GIC CD* insns for setting config", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-23-peter.maydell@linaro.org/mbox/" }, { "id": 2216883, "url": "http://patchwork.ozlabs.org/api/patches/2216883/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-24-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-24-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:18", "name": "[v2,23/65] hw/intc/arm_gicv5: Create backing state for SPIs", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-24-peter.maydell@linaro.org/mbox/" }, { "id": 2216930, "url": "http://patchwork.ozlabs.org/api/patches/2216930/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-25-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-25-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:19", "name": "[v2,24/65] hw/intc/arm_gicv5: Make gicv5_set_* update SPI state", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-25-peter.maydell@linaro.org/mbox/" }, { "id": 2216900, "url": "http://patchwork.ozlabs.org/api/patches/2216900/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-26-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-26-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:20", "name": "[v2,25/65] hw/intc/arm_gicv5: Implement gicv5_request_config()", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-26-peter.maydell@linaro.org/mbox/" }, { "id": 2216915, "url": "http://patchwork.ozlabs.org/api/patches/2216915/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-27-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-27-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:21", "name": "[v2,26/65] target/arm: GICv5 cpuif: Implement GIC CDRCFG and ICC_ICSR_EL1", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-27-peter.maydell@linaro.org/mbox/" }, { "id": 2216899, "url": "http://patchwork.ozlabs.org/api/patches/2216899/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-28-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-28-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:22", "name": "[v2,27/65] hw/intc/arm_gicv5: Implement IRS_SPI_{SELR, STATUSR, CFGR, DOMAINR}", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-28-peter.maydell@linaro.org/mbox/" }, { "id": 2216873, "url": "http://patchwork.ozlabs.org/api/patches/2216873/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-29-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-29-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:23", "name": "[v2,28/65] hw/intc/arm_gicv5: Update SPI state for CLEAR/SET events", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-29-peter.maydell@linaro.org/mbox/" }, { "id": 2216896, "url": "http://patchwork.ozlabs.org/api/patches/2216896/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-30-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-30-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:24", "name": "[v2,29/65] hw/intc/arm_gicv5: Implement IRS_CR0 and IRS_CR1", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-30-peter.maydell@linaro.org/mbox/" }, { "id": 2216869, "url": "http://patchwork.ozlabs.org/api/patches/2216869/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-31-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-31-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:25", "name": "[v2,30/65] hw/intc/arm_gicv5: Implement IRS_SYNCR and IRS_SYNC_STATUSR", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-31-peter.maydell@linaro.org/mbox/" }, { "id": 2216906, "url": "http://patchwork.ozlabs.org/api/patches/2216906/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-32-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-32-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:26", "name": "[v2,31/65] hw/intc/arm_gicv5: Implement IRS_PE_{CR0, SELR, STATUSR}", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-32-peter.maydell@linaro.org/mbox/" }, { "id": 2216890, "url": "http://patchwork.ozlabs.org/api/patches/2216890/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-33-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-33-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:27", "name": "[v2,32/65] hw/intc/arm_gicv5: Implement CoreSight ID registers", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-33-peter.maydell@linaro.org/mbox/" }, { "id": 2216877, "url": "http://patchwork.ozlabs.org/api/patches/2216877/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-34-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-34-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:28", "name": "[v2,33/65] hw/intc/arm_gicv5: Cache pending LPIs in a hash table", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-34-peter.maydell@linaro.org/mbox/" }, { "id": 2216874, "url": "http://patchwork.ozlabs.org/api/patches/2216874/?format=api", "web_url": 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"http://patchwork.ozlabs.org/api/patches/2216892/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-48-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-48-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:42", "name": "[v2,47/65] hw/intc/arm_gicv5: Implement Activate command", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-48-peter.maydell@linaro.org/mbox/" }, { "id": 2216886, "url": "http://patchwork.ozlabs.org/api/patches/2216886/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-49-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-49-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:43", "name": "[v2,48/65] target/arm: GICv5 cpuif: Implement GICR CDIA command", "mbox": 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"[v2,52/65] target/arm: GICv5 cpuif: Signal IRQ or FIQ", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-53-peter.maydell@linaro.org/mbox/" }, { "id": 2216909, "url": "http://patchwork.ozlabs.org/api/patches/2216909/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-54-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-54-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:48", "name": "[v2,53/65] target/arm: Connect internal interrupt sources up as GICv5 PPIs", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-54-peter.maydell@linaro.org/mbox/" }, { "id": 2216903, "url": "http://patchwork.ozlabs.org/api/patches/2216903/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-55-peter.maydell@linaro.org/", "msgid": "<20260327111700.795099-55-peter.maydell@linaro.org>", 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Allow user to select GICv5", "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-66-peter.maydell@linaro.org/mbox/" } ] }