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GET /api/patches/2216912/?format=api
{ "id": 2216912, "url": "http://patchwork.ozlabs.org/api/patches/2216912/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-62-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-62-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:56", "name": "[v2,61/65] hw/arm/virt: Advertise GICv5 in the DTB", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2a6eabb9da1fef6ce4e330fbf7b8dadee4c1ff5b", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-62-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216912/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216912/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=g9HJU6yp;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyvC6q3dz1yFr\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:23:35 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Dm-0001Up-Vi; Fri, 27 Mar 2026 07:19:23 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Ca-0007kV-DU\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:08 -0400", "from mail-wr1-x433.google.com ([2a00:1450:4864:20::433])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CX-0000GE-2n\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:08 -0400", "by mail-wr1-x433.google.com with SMTP id\n ffacd0b85a97d-439b2965d4bso1507118f8f.2\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:18:01 -0700 (PDT)", "from lanath.. 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This binding is final as it is in\nthe upstream Linux kernel as:\nDocumentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/arm/virt.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 68 insertions(+)", "diff": "diff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex b6a04f868b..7a34af766a 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -794,6 +794,72 @@ static void create_v2m(VirtMachineState *vms)\n vms->msi_controller = VIRT_MSI_CTRL_GICV2M;\n }\n \n+static void fdt_add_gicv5_node(VirtMachineState *vms)\n+{\n+ MachineState *ms = MACHINE(vms);\n+ const char *nodename = \"/intc\";\n+ g_autofree char *irsnodename = NULL;\n+ g_autofree uint32_t *cpu_phandles = g_new(uint32_t, ms->smp.cpus);\n+ g_autofree uint16_t *iaffids = g_new(uint16_t, ms->smp.cpus);\n+\n+ vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);\n+ qemu_fdt_setprop_cell(ms->fdt, \"/\", \"interrupt-parent\", vms->gic_phandle);\n+\n+ qemu_fdt_add_subnode(ms->fdt, nodename);\n+ qemu_fdt_setprop_cell(ms->fdt, nodename, \"phandle\", vms->gic_phandle);\n+ qemu_fdt_setprop_string(ms->fdt, nodename, \"compatible\", \"arm,gic-v5\");\n+ qemu_fdt_setprop_cell(ms->fdt, nodename, \"#interrupt-cells\", 3);\n+ qemu_fdt_setprop(ms->fdt, nodename, \"interrupt-controller\", NULL, 0);\n+ qemu_fdt_setprop_cell(ms->fdt, nodename, \"#address-cells\", 0x2);\n+ qemu_fdt_setprop_cell(ms->fdt, nodename, \"#size-cells\", 0x2);\n+ qemu_fdt_setprop(ms->fdt, nodename, \"ranges\", NULL, 0);\n+\n+ /* The IRS node is a child of the top level /intc node */\n+ irsnodename = g_strdup_printf(\"%s/irs@%\" PRIx64,\n+ nodename,\n+ vms->memmap[VIRT_GICV5_IRS_NS].base);\n+ qemu_fdt_add_subnode(ms->fdt, irsnodename);\n+ qemu_fdt_setprop_string(ms->fdt, irsnodename, \"compatible\",\n+ \"arm,gic-v5-irs\");\n+ /*\n+ * \"reg-names\" describes the frames whose address/size is in \"reg\";\n+ * at the moment we have only the NS config register frame.\n+ */\n+ qemu_fdt_setprop_string(ms->fdt, irsnodename, \"reg-names\", \"ns-config\");\n+ qemu_fdt_setprop_sized_cells(ms->fdt, irsnodename, \"reg\",\n+ 2, vms->memmap[VIRT_GICV5_IRS_NS].base,\n+ 2, vms->memmap[VIRT_GICV5_IRS_NS].size);\n+ qemu_fdt_setprop_cell(ms->fdt, irsnodename, \"#address-cells\", 0x2);\n+ qemu_fdt_setprop_cell(ms->fdt, irsnodename, \"#size-cells\", 0x2);\n+ qemu_fdt_setprop(ms->fdt, irsnodename, \"ranges\", NULL, 0);\n+\n+ /*\n+ * The \"cpus\" property is an array of phandles to the CPUs, and\n+ * \"iaffids\" is an array of uint16 IAFFIDs. For virt, our IAFFIDs\n+ * are the CPU indexes. This function is called after\n+ * fdt_add_cpu_nodes(), which allocates the cpu_phandles array.\n+ */\n+ assert(vms->cpu_phandles);\n+ for (int i = 0; i < ms->smp.cpus; i++) {\n+ /*\n+ * We have to byteswap each element here because we're setting the\n+ * whole property value at once as a lump of raw data, not via a\n+ * helper like qemu_fdt_setprop_cell() that does the swapping for us.\n+ */\n+ cpu_phandles[i] = cpu_to_be32(vms->cpu_phandles[i]);\n+ iaffids[i] = cpu_to_be16(i);\n+ }\n+ qemu_fdt_setprop(ms->fdt, irsnodename, \"cpus\", cpu_phandles,\n+ ms->smp.cpus * sizeof(*cpu_phandles));\n+ qemu_fdt_setprop(ms->fdt, irsnodename, \"arm,iaffids\", iaffids,\n+ ms->smp.cpus * sizeof(*iaffids));\n+\n+ /*\n+ * When we implement the GICv5 IRS, it gets a DTB node which is a\n+ * child of the IRS node.\n+ */\n+}\n+\n static void create_gicv5(VirtMachineState *vms, MemoryRegion *mem)\n {\n MachineState *ms = MACHINE(vms);\n@@ -835,6 +901,8 @@ static void create_gicv5(VirtMachineState *vms, MemoryRegion *mem)\n * that information is communicated directly between a GICv5 IRS and\n * the GICv5 CPU interface via our equivalent of the stream protocol.\n */\n+\n+ fdt_add_gicv5_node(vms);\n }\n \n /*\n", "prefixes": [ "v2", "61/65" ] }