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GET /api/patches/2216921/?format=api
{ "id": 2216921, "url": "http://patchwork.ozlabs.org/api/patches/2216921/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-22-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-22-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:16", "name": "[v2,21/65] hw/intc/arm_gicv5: Implement remaining set-config functions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "306210276520c6a936b2821b4f346dbbd81518dc", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-22-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216921/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216921/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=gwBiU4nW;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhywk56JMz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:24:54 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65C0-0006jq-UD; Fri, 27 Mar 2026 07:17:32 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bu-0006ZR-Ar\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:26 -0400", "from mail-wm1-x336.google.com ([2a00:1450:4864:20::336])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Br-0007wO-U9\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:26 -0400", "by mail-wm1-x336.google.com with SMTP id\n 5b1f17b1804b1-4852b81c73aso17685745e9.3\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:23 -0700 (PDT)", "from lanath.. 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These\nwork exactly like SetPriority: the IRS looks up the L2TE and updates\nthe corresponding field in it with the new value.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5.c | 152 +++++++++++++++++++++++++++++\n hw/intc/trace-events | 4 +\n include/hw/intc/arm_gicv5_stream.h | 68 +++++++++++++\n include/hw/intc/arm_gicv5_types.h | 15 +++\n 4 files changed, 239 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex 7d654a91e6..d1eb96fce0 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -497,6 +497,158 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id, uint8_t priority,\n }\n }\n \n+void gicv5_set_enabled(GICv5Common *cs, uint32_t id, bool enabled,\n+ GICv5Domain domain, GICv5IntType type, bool virtual)\n+{\n+ GICv5 *s = ARM_GICV5(cs);\n+\n+ trace_gicv5_set_enabled(domain_name[domain], inttype_name(type), virtual,\n+ id, enabled);\n+ if (virtual) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_enabled: tried to set \"\n+ \"enable state of a virtual interrupt\\n\");\n+ return;\n+ }\n+\n+ switch (type) {\n+ case GICV5_LPI:\n+ {\n+ const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain];\n+ L2_ISTE_Handle h;\n+ uint32_t *l2_iste_p = get_l2_iste(cs, cfg, id, &h);\n+\n+ if (!l2_iste_p) {\n+ return;\n+ }\n+ *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, ENABLE, enabled);\n+ put_l2_iste(cs, cfg, &h);\n+ break;\n+ }\n+ default:\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_enabled: tried to set \"\n+ \"enable state of bad interrupt type %d\\n\", type);\n+ return;\n+ }\n+}\n+\n+void gicv5_set_pending(GICv5Common *cs, uint32_t id, bool pending,\n+ GICv5Domain domain, GICv5IntType type, bool virtual)\n+{\n+ GICv5 *s = ARM_GICV5(cs);\n+\n+ trace_gicv5_set_pending(domain_name[domain], inttype_name(type), virtual,\n+ id, pending);\n+ if (virtual) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_pending: tried to set \"\n+ \"pending state of a virtual interrupt\\n\");\n+ return;\n+ }\n+\n+ switch (type) {\n+ case GICV5_LPI:\n+ {\n+ const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain];\n+ L2_ISTE_Handle h;\n+ uint32_t *l2_iste_p = get_l2_iste(cs, cfg, id, &h);\n+\n+ if (!l2_iste_p) {\n+ return;\n+ }\n+ *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, PENDING, pending);\n+ put_l2_iste(cs, cfg, &h);\n+ break;\n+ }\n+ default:\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_pending: tried to set \"\n+ \"pending state of bad interrupt type %d\\n\", type);\n+ return;\n+ }\n+}\n+\n+void gicv5_set_handling(GICv5Common *cs, uint32_t id,\n+ GICv5HandlingMode handling, GICv5Domain domain,\n+ GICv5IntType type, bool virtual)\n+{\n+ GICv5 *s = ARM_GICV5(cs);\n+\n+ trace_gicv5_set_handling(domain_name[domain], inttype_name(type), virtual,\n+ id, handling);\n+ if (virtual) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_handling: tried to set \"\n+ \"handling mode of a virtual interrupt\\n\");\n+ return;\n+ }\n+\n+ switch (type) {\n+ case GICV5_LPI:\n+ {\n+ const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain];\n+ L2_ISTE_Handle h;\n+ uint32_t *l2_iste_p = get_l2_iste(cs, cfg, id, &h);\n+\n+ if (!l2_iste_p) {\n+ return;\n+ }\n+ *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, HM, handling);\n+ put_l2_iste(cs, cfg, &h);\n+ break;\n+ }\n+ default:\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_handling: tried to set \"\n+ \"handling mode of bad interrupt type %d\\n\", type);\n+ return;\n+ }\n+}\n+\n+void gicv5_set_target(GICv5Common *cs, uint32_t id, uint32_t iaffid,\n+ GICv5RoutingMode irm, GICv5Domain domain,\n+ GICv5IntType type, bool virtual)\n+{\n+ GICv5 *s = ARM_GICV5(cs);\n+\n+ trace_gicv5_set_target(domain_name[domain], inttype_name(type), virtual,\n+ id, iaffid, irm);\n+ if (virtual) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_target: tried to set \"\n+ \"target of a virtual interrupt\\n\");\n+ return;\n+ }\n+ if (irm != GICV5_TARGETED) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_target: tried to set \"\n+ \"1-of-N routing\\n\");\n+ /*\n+ * In the cpuif insn \"GIC CDAFF\", IRM is RES0 for a GIC which\n+ * does not support 1-of-N routing. So warn, and fall through\n+ * to treat IRM=1 the same as IRM=0.\n+ */\n+ }\n+\n+ switch (type) {\n+ case GICV5_LPI:\n+ {\n+ const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain];\n+ L2_ISTE_Handle h;\n+ uint32_t *l2_iste_p = get_l2_iste(cs, cfg, id, &h);\n+\n+ if (!l2_iste_p) {\n+ return;\n+ }\n+ /*\n+ * For QEMU we do not implement 1-of-N routing, and so\n+ * L2_ISTE.IRM is RES0. We never read it, and we can skip\n+ * explicitly writing it to zero here.\n+ */\n+ *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, IAFFID, iaffid);\n+ put_l2_iste(cs, cfg, &h);\n+ break;\n+ }\n+ default:\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_target: tried to set \"\n+ \"target of bad interrupt type %d\\n\", type);\n+ return;\n+ }\n+}\n+\n static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t value)\n {\n GICv5Common *cs = ARM_GICV5_COMMON(s);\ndiff --git a/hw/intc/trace-events b/hw/intc/trace-events\nindex 42f5e73d54..37ca6e8e12 100644\n--- a/hw/intc/trace-events\n+++ b/hw/intc/trace-events\n@@ -236,6 +236,10 @@ gicv5_spi(uint32_t id, int level) \"GICv5 SPI ID %u asserted at level %d\"\n gicv5_ist_valid(const char *domain, uint64_t base, uint8_t id_bits, uint8_t l2_idx_bits, uint8_t istsz, bool structure) \"GICv5 IRS %s IST now valid: base 0x%\" PRIx64 \" id_bits %u l2_idx_bits %u IST entry size %u 2-level %d\"\n gicv5_ist_invalid(const char *domain) \"GICv5 IRS %s IST no longer valid\"\n gicv5_set_priority(const char *domain, const char *type, bool virtual, uint32_t id, uint8_t priority) \"GICv5 IRS SetPriority %s %s virtual:%d ID %u prio %u\"\n+gicv5_set_enabled(const char *domain, const char *type, bool virtual, uint32_t id, bool enabled) \"GICv5 IRS SetEnabled %s %s virtual:%d ID %u enabled %d\"\n+gicv5_set_pending(const char *domain, const char *type, bool virtual, uint32_t id, bool pending) \"GICv5 IRS SetPending %s %s virtual:%d ID %u pending %d\"\n+gicv5_set_handling(const char *domain, const char *type, bool virtual, uint32_t id, int handling) \"GICv5 IRS SetHandling %s %s virtual:%d ID %u handling %d\"\n+gicv5_set_target(const char *domain, const char *type, bool virtual, uint32_t id, uint32_t iaffid, int irm) \"GICv5 IRS SetTarget %s %s virtual:%d ID %u IAFFID %u routingmode %d\"\n \n # arm_gicv5_common.c\n gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base, uint32_t spi_irs_range, uint32_t spi_range) \"GICv5 IRS realized: IRS ID %u, %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u\"\ndiff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5_stream.h\nindex e1649cbb40..af2e1851c2 100644\n--- a/include/hw/intc/arm_gicv5_stream.h\n+++ b/include/hw/intc/arm_gicv5_stream.h\n@@ -58,4 +58,72 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id,\n uint8_t priority, GICv5Domain domain,\n GICv5IntType type, bool virtual);\n \n+/**\n+ * gicv5_set_enabled\n+ * @cs: GIC IRS to send command to\n+ * @id: interrupt ID\n+ * @enabled: new enabled state\n+ * @domain: interrupt Domain to act on\n+ * @type: interrupt type (LPI or SPI)\n+ * @virtual: true if this is a virtual interrupt\n+ *\n+ * Set enabled state of an interrupt; matches stream interface\n+ * SetEnabled command from CPUIF to IRS. There is no report back of\n+ * success/failure to the CPUIF in the protocol.\n+ */\n+void gicv5_set_enabled(GICv5Common *cs, uint32_t id,\n+ bool enabled, GICv5Domain domain,\n+ GICv5IntType type, bool virtual);\n+\n+/**\n+ * gicv5_set_pending\n+ * @cs: GIC IRS to send command to\n+ * @id: interrupt ID\n+ * @pending: new pending state\n+ * @domain: interrupt Domain to act on\n+ * @type: interrupt type (LPI or SPI)\n+ * @virtual: true if this is a virtual interrupt\n+ *\n+ * Set pending state of an interrupt; matches stream interface\n+ * SetPending command from CPUIF to IRS. There is no report back of\n+ * success/failure to the CPUIF in the protocol.\n+ */\n+void gicv5_set_pending(GICv5Common *cs, uint32_t id,\n+ bool pending, GICv5Domain domain,\n+ GICv5IntType type, bool virtual);\n+\n+/**\n+ * gicv5_set_handling\n+ * @cs: GIC IRS to send command to\n+ * @id: interrupt ID\n+ * @handling: new handling mode\n+ * @domain: interrupt Domain to act on\n+ * @type: interrupt type (LPI or SPI)\n+ * @virtual: true if this is a virtual interrupt\n+ *\n+ * Set handling mode of an interrupt (edge/level); matches stream\n+ * interface SetHandling command from CPUIF to IRS. There is no report\n+ * back of success/failure to the CPUIF in the protocol.\n+ */\n+void gicv5_set_handling(GICv5Common *cs, uint32_t id,\n+ GICv5HandlingMode handling, GICv5Domain domain,\n+ GICv5IntType type, bool virtual);\n+\n+/**\n+ * gicv5_set_target\n+ * @cs: GIC IRS to send command to\n+ * @id: interrupt ID\n+ * @iaffid: new target PE's interrupt affinity\n+ * @irm: interrupt routing mode (targeted vs 1-of-N)\n+ * @domain: interrupt Domain to act on\n+ * @type: interrupt type (LPI or SPI)\n+ * @virtual: true if this is a virtual interrupt\n+ *\n+ * Set handling mode of an interrupt (edge/level); matches stream\n+ * interface SetHandling command from CPUIF to IRS. There is no report\n+ * back of success/failure to the CPUIF in the protocol.\n+ */\n+void gicv5_set_target(GICv5Common *cs, uint32_t id, uint32_t iaffid,\n+ GICv5RoutingMode irm, GICv5Domain domain,\n+ GICv5IntType type, bool virtual);\n #endif\ndiff --git a/include/hw/intc/arm_gicv5_types.h b/include/hw/intc/arm_gicv5_types.h\nindex e2b937fe62..20de5b3f46 100644\n--- a/include/hw/intc/arm_gicv5_types.h\n+++ b/include/hw/intc/arm_gicv5_types.h\n@@ -55,4 +55,19 @@ typedef enum GICv5IntType {\n GICV5_SPI = 3,\n } GICv5IntType;\n \n+/* Interrupt handling mode (same encoding as L2_ISTE.HM) */\n+typedef enum GICv5HandlingMode {\n+ GICV5_EDGE = 0,\n+ GICV5_LEVEL = 1,\n+} GICv5HandlingMode;\n+\n+/*\n+ * Interrupt routing mode (same encoding as L2_ISTE.IRM).\n+ * Note that 1-of-N support is option and QEMU does not implement it.\n+ */\n+typedef enum GICv5RoutingMode {\n+ GICV5_TARGETED = 0,\n+ GICV5_1OFN = 1,\n+} GICv5RoutingMode;\n+\n #endif\n", "prefixes": [ "v2", "21/65" ] }