Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2216878/?format=api
{ "id": 2216878, "url": "http://patchwork.ozlabs.org/api/patches/2216878/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-36-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-36-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:30", "name": "[v2,35/65] target/arm: GICv5 cpuif: Implement ICC_IDR0_EL1", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "26191bd6a55e255f71268a15b0b1c6254331b759", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-36-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216878/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216878/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=YqXGija7;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhypR6jL6z1y1x\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:19:27 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65CA-0006xw-1D; Fri, 27 Mar 2026 07:17:42 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C7-0006sy-0F\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:39 -0400", "from mail-wr1-x435.google.com ([2a00:1450:4864:20::435])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C5-00088z-7Y\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:38 -0400", "by mail-wr1-x435.google.com with SMTP id\n ffacd0b85a97d-439d8df7620so1409170f8f.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:36 -0700 (PDT)", "from lanath.. (wildly.archaic.org.uk. [81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.34\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 27 Mar 2026 04:17:35 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1774610256; x=1775215056; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=ajCMEb2lQLuc5DJ03lNLJ9KK+fIl70fxwg3ayKyNDHE=;\n b=YqXGija7U9DkUVtKOoXH4TE3QFhB4rl0WbIFdHGgb31A2uMIu6pQgYgzqCz8NA4C2P\n j+A1KvapnabGbh/gIquF0JJYMHEg1Jc94e7MXv1yRoYIGbEosYbcbGgmSP5E9cRIZ6do\n WGYRIJOPYYqLYTnp1aPUImxL33uD8KaIm3KDok1sJ+SkIxVfcyBMNbZro/UMfZ/2njDL\n /eFW8baayZTwJWeaPfmWUMe5/UvRsmUbRARkzjAhHaRIBYFVWAZknYD/u99csoBlvmke\n QdF8zrWqJRfOfTqcy6A3Bug+7/Ls0dtekf4uQtrXEheLKNQMQM9RhyLnWjTwNeJk73wC\n a4kw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774610256; x=1775215056;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=ajCMEb2lQLuc5DJ03lNLJ9KK+fIl70fxwg3ayKyNDHE=;\n b=dJxBGKa3KjpJwKQ6D4LmipFmX36M9xLez68VYPgMVTtcKOqAgj8TshjNMCNxVJsgxB\n +hi/r/41e0OJi7xOXmee1DqYOPaUjGHcoN7qmus+yv2uHBEP7LcKtGOHtwQHH/X+njOb\n ELbQg9yIotvK+Oi52vBZsIvkmtz+3toaAdmN3y5jx5FOcLey75iQzz33LXUi8BGrL+mV\n d3wN2aUJpzSyvLBt/+la9BTdXP0o8GAslNgv0xXonOtAodBjneKQsF9WTBjo9hmBZn/L\n WlStiNKXxeo6q7XCmzx85v/7MHWXubXhQ+v6txcoLqh0MYO1PjWZsQn8iuQSsMbsEU9L\n WokA==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCWIw+pa0K3gNlFd6mBtOWHDwGMwwlJWwOW3kbTAffFdGbkHNqEIlJyRg6Q3e5gP0y/LIAFmvZg2T+Td@nongnu.org", "X-Gm-Message-State": "AOJu0YyHW4u/OG9FR9iMiZa5EAjU/7R6UbgBfv8OHYxYzsu4xk8wl3+x\n d3isJsX4dDV+DJQHK/k3rnmLBdiwXfl8ygUijq5ScsVKQvrkwoWNmul+UZi3ih+IL4AHzg5M+u5\n L3gv9ssQ=", "X-Gm-Gg": "ATEYQzyjLGn0ky++k/lF+ioxYHxWJFQDjJjNXb8fB0JufRjz75ZMcKDH4y7Rh+sh3H6\n XZNlpqoo3rkoQybwOvtnCYQ/8hLBqJCcIcn34PFeq+BDA9H9E4OBXw8y4EgopQZfVkvtFyhKg4B\n x4Lf2N1QevJkT1nOzG0fA0zV79dTCoqNacPhWRwmYE31hrPVvl2LysCrC05pPqeDcrwM5ENu/9A\n frR9R0aUn9uGaX3Zt3ub+aMEXStkhEk8AYCEcaDwr8F2SLu1RPZFBUsaNxxoSrEvBb3Vz0fehy6\n gaQ+MBJnrdWQxut+K6iGrmSSIRH8p8AOsyXrXz8tfu/4M1l6UI/Z2UoTgeupB3TUsp/OhP91GF/\n 0KUnbS+qEEZLFHOr6RpAoJh4ZMV0frJ0fMQKtsZNuPOECvPYSb5CSPNqZD8oaVHWGv8tjcHr1ww\n BQLwOAhRV+B0Q1G0pk3P5OB0v/Zj9qJvO+Vc/BL2ds3EJxZ7kCoGXOyz3RVXFSk3xcJ+HdA4Tab\n bjirmWeZ8C8u6NB1RY4Bq3MhEDWTcg=", "X-Received": "by 2002:a05:6000:2892:b0:439:b744:c601 with SMTP id\n ffacd0b85a97d-43b9ea638d1mr3375657f8f.40.1774610255710;\n Fri, 27 Mar 2026 04:17:35 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Jonathan Cameron <jonathan.cameron@huawei.com>", "Subject": "[PATCH v2 35/65] target/arm: GICv5 cpuif: Implement ICC_IDR0_EL1", "Date": "Fri, 27 Mar 2026 11:16:30 +0000", "Message-ID": "<20260327111700.795099-36-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327111700.795099-1-peter.maydell@linaro.org>", "References": "<20260327111700.795099-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::435;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "ICC_IDR0_EL1 is an identification register; we can implement this as\na simple constant value.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/tcg/gicv5-cpuif.c | 17 +++++++++++++++++\n 1 file changed, 17 insertions(+)", "diff": "diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 005e2fa8d2..497c09474b 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -38,6 +38,18 @@ FIELD(GIC_CDHM, HM, 32, 1)\n FIELD(GIC_CDRCFG, ID, 0, 24)\n FIELD(GIC_CDRCFG, TYPE, 29, 3)\n \n+FIELD(ICC_IDR0_EL1, ID_BITS, 0, 4)\n+FIELD(ICC_IDR0_EL1, PRI_BITS, 4, 4)\n+FIELD(ICC_IDR0_EL1, GCIE_LEGACY, 8, 4)\n+\n+/*\n+ * We implement 24 bits of interrupt ID, the mandated 5 bits of priority,\n+ * and no legacy GICv3.3 vcpu interface (yet)\n+ */\n+#define QEMU_ICC_IDR0 \\\n+ ((4 << R_ICC_IDR0_EL1_PRI_BITS_SHIFT) | \\\n+ (1 << R_ICC_IDR0_EL1_ID_BITS_SHIFT))\n+\n static GICv5Common *gicv5_get_gic(CPUARMState *env)\n {\n return env->gicv5state;\n@@ -220,6 +232,11 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n .writefn = gic_cdhm_write,\n },\n+ { .name = \"ICC_IDR0_EL1\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 2,\n+ .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,\n+ .resetvalue = QEMU_ICC_IDR0,\n+ },\n { .name = \"ICC_ICSR_EL1\", .state = ARM_CP_STATE_AA64,\n .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 4,\n .access = PL1_RW, .type = ARM_CP_NO_RAW,\n", "prefixes": [ "v2", "35/65" ] }