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GET /api/patches/2216907/?format=api
{ "id": 2216907, "url": "http://patchwork.ozlabs.org/api/patches/2216907/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-4-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-4-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:15:58", "name": "[v2,03/65] hw/intc: Skeleton of GICv5 IRS classes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0908b9e949160fbdc49a60b4b702b9cf5b4cdf58", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-4-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216907/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216907/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=q40FJV2j;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhytw1LzMz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:23:20 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Bi-0006OI-7Q; Fri, 27 Mar 2026 07:17:14 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bc-0006LT-TP\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:08 -0400", "from mail-wm1-x333.google.com ([2a00:1450:4864:20::333])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Ba-0007XU-FD\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:08 -0400", "by mail-wm1-x333.google.com with SMTP id\n 5b1f17b1804b1-48538c5956bso18874515e9.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:05 -0700 (PDT)", "from lanath.. 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Since the IRS is the main (and only\nnon-optional) part of the GICv5 outside the CPU, we call it simply\n\"GICv5\", in line with how we've handled the GICv3.\n\nSince we're definitely going to need to have support for KVM VMs\nwhere we present the guest with a GICv5, we use the same split\nbetween an abstract \"common\" and a concrete specific-to-TCG child\nclass that we have for the various GICv3 components. This avoids\nhaving to refactor out the base class later.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/Kconfig | 4 +++\n hw/intc/arm_gicv5.c | 39 ++++++++++++++++++++++++++++++\n hw/intc/arm_gicv5_common.c | 31 ++++++++++++++++++++++++\n hw/intc/meson.build | 4 +++\n include/hw/intc/arm_gicv5.h | 32 ++++++++++++++++++++++++\n include/hw/intc/arm_gicv5_common.h | 31 ++++++++++++++++++++++++\n 6 files changed, 141 insertions(+)\n create mode 100644 hw/intc/arm_gicv5.c\n create mode 100644 hw/intc/arm_gicv5_common.c\n create mode 100644 include/hw/intc/arm_gicv5.h\n create mode 100644 include/hw/intc/arm_gicv5_common.h", "diff": "diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig\nindex 9f456d7e43..a3241fc1eb 100644\n--- a/hw/intc/Kconfig\n+++ b/hw/intc/Kconfig\n@@ -35,6 +35,10 @@ config ARM_GIC_KVM\n bool\n depends on ARM_GIC && KVM\n \n+config ARM_GICV5\n+ bool\n+ select MSI_NONBROKEN\n+\n config XICS\n bool\n \ndiff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nnew file mode 100644\nindex 0000000000..f9dab710d3\n--- /dev/null\n+++ b/hw/intc/arm_gicv5.c\n@@ -0,0 +1,39 @@\n+/*\n+ * ARM GICv5 emulation: Interrupt Routing Service (IRS)\n+ *\n+ * Copyright (c) 2025 Linaro Limited\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"hw/intc/arm_gicv5.h\"\n+\n+OBJECT_DEFINE_TYPE(GICv5, gicv5, ARM_GICV5, ARM_GICV5_COMMON)\n+\n+static void gicv5_reset_hold(Object *obj, ResetType type)\n+{\n+ GICv5 *s = ARM_GICV5(obj);\n+ GICv5Class *c = ARM_GICV5_GET_CLASS(s);\n+\n+ if (c->parent_phases.hold) {\n+ c->parent_phases.hold(obj, type);\n+ }\n+}\n+\n+static void gicv5_init(Object *obj)\n+{\n+}\n+\n+static void gicv5_finalize(Object *obj)\n+{\n+}\n+\n+static void gicv5_class_init(ObjectClass *oc, const void *data)\n+{\n+ ResettableClass *rc = RESETTABLE_CLASS(oc);\n+ GICv5Class *gc = ARM_GICV5_CLASS(oc);\n+\n+ resettable_class_set_parent_phases(rc, NULL, gicv5_reset_hold, NULL,\n+ &gc->parent_phases);\n+}\ndiff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c\nnew file mode 100644\nindex 0000000000..b0194f7f26\n--- /dev/null\n+++ b/hw/intc/arm_gicv5_common.c\n@@ -0,0 +1,31 @@\n+/*\n+ * Common base class for GICv5 IRS\n+ *\n+ * Copyright (c) 2025 Linaro Limited\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"hw/intc/arm_gicv5_common.h\"\n+\n+OBJECT_DEFINE_ABSTRACT_TYPE(GICv5Common, gicv5_common, ARM_GICV5_COMMON, SYS_BUS_DEVICE)\n+\n+static void gicv5_common_reset_hold(Object *obj, ResetType type)\n+{\n+}\n+\n+static void gicv5_common_init(Object *obj)\n+{\n+}\n+\n+static void gicv5_common_finalize(Object *obj)\n+{\n+}\n+\n+static void gicv5_common_class_init(ObjectClass *oc, const void *data)\n+{\n+ ResettableClass *rc = RESETTABLE_CLASS(oc);\n+\n+ rc->phases.hold = gicv5_common_reset_hold;\n+}\ndiff --git a/hw/intc/meson.build b/hw/intc/meson.build\nindex 96742df090..e4ddc5107f 100644\n--- a/hw/intc/meson.build\n+++ b/hw/intc/meson.build\n@@ -12,6 +12,10 @@ system_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files(\n 'arm_gicv3_its.c',\n 'arm_gicv3_redist.c',\n ))\n+system_ss.add(when: 'CONFIG_ARM_GICV5', if_true: files(\n+ 'arm_gicv5_common.c',\n+ 'arm_gicv5.c',\n+))\n system_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))\n system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_vic.c'))\n system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_intc.c'))\ndiff --git a/include/hw/intc/arm_gicv5.h b/include/hw/intc/arm_gicv5.h\nnew file mode 100644\nindex 0000000000..3cd9652f6f\n--- /dev/null\n+++ b/include/hw/intc/arm_gicv5.h\n@@ -0,0 +1,32 @@\n+/*\n+ * ARM GICv5 emulation: Interrupt Routing Service (IRS)\n+ *\n+ * Copyright (c) 2025 Linaro Limited\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HW_INTC_ARM_GICV5_H\n+#define HW_INTC_ARM_GICV5_H\n+\n+#include \"qom/object.h\"\n+#include \"hw/core/sysbus.h\"\n+#include \"hw/intc/arm_gicv5_common.h\"\n+\n+#define TYPE_ARM_GICV5 \"arm-gicv5\"\n+\n+OBJECT_DECLARE_TYPE(GICv5, GICv5Class, ARM_GICV5)\n+\n+/*\n+ * This class is for TCG-specific state for the GICv5.\n+ */\n+struct GICv5 {\n+ GICv5Common parent_obj;\n+};\n+\n+struct GICv5Class {\n+ GICv5CommonClass parent_class;\n+ ResettablePhases parent_phases;\n+};\n+\n+#endif\ndiff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5_common.h\nnew file mode 100644\nindex 0000000000..d2243c7660\n--- /dev/null\n+++ b/include/hw/intc/arm_gicv5_common.h\n@@ -0,0 +1,31 @@\n+/*\n+ * Common base class for GICv5 IRS\n+ *\n+ * Copyright (c) 2025 Linaro Limited\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HW_INTC_ARM_GICV5_COMMON_H\n+#define HW_INTC_ARM_GICV5_COMMON_H\n+\n+#include \"qom/object.h\"\n+#include \"hw/core/sysbus.h\"\n+\n+#define TYPE_ARM_GICV5_COMMON \"arm-gicv5-common\"\n+\n+OBJECT_DECLARE_TYPE(GICv5Common, GICv5CommonClass, ARM_GICV5_COMMON)\n+\n+/*\n+ * This class is for common state that will eventually be shared\n+ * between TCG and KVM implementations of the GICv5.\n+ */\n+struct GICv5Common {\n+ SysBusDevice parent_obj;\n+};\n+\n+struct GICv5CommonClass {\n+ SysBusDeviceClass parent_class;\n+};\n+\n+#endif\n", "prefixes": [ "v2", "03/65" ] }