Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2216931/?format=api
{ "id": 2216931, "url": "http://patchwork.ozlabs.org/api/patches/2216931/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-17-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-17-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:11", "name": "[v2,16/65] hw/intc/arm_gicv5: Implement IRS_IST_{BASER, STATUSR, CFGR}", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "95bc1f71a57bc5c8bc542318becede7a2c90a124", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-17-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216931/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216931/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=MDXy222S;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyy04T8qz1yFr\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:26:00 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Bs-0006Y9-La; Fri, 27 Mar 2026 07:17:24 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bp-0006Th-BG\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:21 -0400", "from mail-wr1-x432.google.com ([2a00:1450:4864:20::432])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bm-0007tz-TG\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:21 -0400", "by mail-wr1-x432.google.com with SMTP id\n ffacd0b85a97d-43b41b545d9so2036496f8f.2\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:18 -0700 (PDT)", "from lanath.. (wildly.archaic.org.uk. [81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.16\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 27 Mar 2026 04:17:16 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1774610237; x=1775215037; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=Bo1tMGJjf8413y4VWnCIE2KG4+bnE/ZHqBVrYM1R3f8=;\n b=MDXy222SaSW1Cb3UqWQ5rcghnYh5QMkTGQn79/3WxAtmUt01K6HILkXsY4ht6pw7GC\n f04m6ulQisNGczXB7/EulGqGCjUtuzu3YKJMmac/nYBfsNA6KfrH4o4KTnh2pG9Xpen2\n LwecPOVzQOFM16W9Vy6U1uMd0ILFAD/SngoKVPhsGNFViiORU8Ny+PGlQD5X1Ep/QwAf\n YQlX4Zt2L93emM6+MkxbdTZMAWhwDe4S8thFX9NnuIqLieeujkD8vGOIPTdD+atXo+5f\n Qmhs0hTMDOxwTnV4n9ETKyMF+7a/9I2L2iHU/qL/WzdrqNdsLOxrJgogCr5IQF3lOO6O\n s2nQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774610237; x=1775215037;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=Bo1tMGJjf8413y4VWnCIE2KG4+bnE/ZHqBVrYM1R3f8=;\n b=WxF9PEvBpYyeK7xwZXdN8Qp3ScsyjVshKIvFGJSXVE6+ZkoPThdc9RTCHGO3QdP+Cw\n 0yErmAmlmryeUeKYLlWNX1Xo/71jgk1f3MfoWkoyCgMRGhrk7qm795bbm0VCQ7k1bEtQ\n C09S7q7+Klq6hYJjs/P1EF1TH5QeCjMEjLQ520VXRcBD69NbDCWAUU+FOqPvuvpidUYV\n G025t2/jKY3k1DHu3PDbTKaGCr/0PFUqRX9pgw7A46bZVCA2HU6ZoXR6F5YU51fd8t/S\n k+7DJ9M3LuI1QDgDoJSYTkHFBy1W/79gSY/9DnCuLCKaggloMm9qiyBu2Gg9Xg2BZE3u\n 7/4A==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCWJVn5No8L/6E9c+tLmZj+LoVXXWSl+KZLJbRPdro/ZtJdFu/aDRjNyZqfafLFpVvytFiv11wIenSqU@nongnu.org", "X-Gm-Message-State": "AOJu0Yx4nBBV87zdHPW5qblEMW+15sDPYdV4JqfNno1C2F+Q4ANTrdHR\n cbatUxWvhcHYkDOptNQzi8Upmb8MqCQ7sxaCw8PCJvLGFgWLNkeMb/DxGLS0MEnvu9JPgh2BmNL\n HasteibU=", "X-Gm-Gg": "ATEYQzz3lgpIT/kfuuMlRbnJ910/1TIMpKEIwLlaCZuelOVFnwfWu8eQ09OMKvtAlmG\n sXbXM2e9XKEfdC4UQMI5NXj5jXPTDNjKn4QgDnlt3+BtLDxGiRIgSvqs+DrhjAhqkZK0cFZR0yn\n Ja9OEqpnghVyq+g7h0zs18F3wOxr1HFeuTQ0hXzKkkCM/ekg2+OckwfeURDIyGnpC5vg6lxb8gq\n NUjTyEylQCqKJMlAaGqPDUhzusnrXvg/1H6700DXt09by2ZyB4CyJ0PifdKIcYUs180xaOsYwO6\n lrFlPMQoGbUhlPQ0+NK1Et12j68Ph/y1rg6pjAQOMht3TcjXho0kqsgBgqNQtU7zQRaBviQtVEr\n vogPgxLs2fngQaZ9gBA5cC4blfBbn86lOQdkMzdVsRRMtq7+Tu16sPSkyk2wkrsnk4LEgd2ArZL\n vvmVJ4bAyqjArKQq4tWns+vs0E5/3BeWAJLi9pW6xLFRww3a0Y2hznBvgoHOttKIavyXY9r7m80\n NfW8wxWCMQe7XlvYkxI2bwqbkRiH48=", "X-Received": "by 2002:a05:6000:2207:b0:439:b7c9:2ef1 with SMTP id\n ffacd0b85a97d-43b9e9ea728mr3197231f8f.20.1774610237142;\n Fri, 27 Mar 2026 04:17:17 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Jonathan Cameron <jonathan.cameron@huawei.com>", "Subject": "[PATCH v2 16/65] hw/intc/arm_gicv5: Implement IRS_IST_{BASER,\n STATUSR,\n CFGR}", "Date": "Fri, 27 Mar 2026 11:16:11 +0000", "Message-ID": "<20260327111700.795099-17-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327111700.795099-1-peter.maydell@linaro.org>", "References": "<20260327111700.795099-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::432;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Implement the three registers that handle configuration of the\ninterrupt status table for physical LPIs:\n\n * IRS_IST_BASER holds the base address of the table, and\n has the VALID bit that tells the IRS to start using the config\n * IRS_IST_CFGR has all the other config data for the table\n * IRS_IST_STATUSR has the IDLE bit that tells software when\n updates to IRS_IST_BASER have taken effect\n\nImplement these registers. Note that neither BASER nor CFGR can be\nwritten when VALID == 1, except to clear the VALID bit.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5.c | 74 ++++++++++++++++++++++++++++++\n hw/intc/arm_gicv5_common.c | 4 ++\n include/hw/intc/arm_gicv5_common.h | 3 ++\n 3 files changed, 81 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex 250925f004..cbb35c0270 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -265,6 +265,24 @@ REG64(IRS_SWERR_SYNDROMER0, 0x3c8)\n REG64(IRS_SWERR_SYNDROMER1, 0x3d0)\n FIELD(IRS_SWERR_SYNDROMER2, ADDR, 3, 53)\n \n+static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t value)\n+{\n+ GICv5Common *cs = ARM_GICV5_COMMON(s);\n+\n+ if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) {\n+ /* If VALID is set, ADDR is RO and we can only update VALID */\n+ bool valid = FIELD_EX64(value, IRS_IST_BASER, VALID);\n+ if (valid) {\n+ /* Ignore 1->1 transition */\n+ return;\n+ }\n+ cs->irs_ist_baser[domain] = FIELD_DP64(cs->irs_ist_baser[domain],\n+ IRS_IST_BASER, VALID, valid);\n+ return;\n+ }\n+ cs->irs_ist_baser[domain] = value;\n+}\n+\n static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,\n uint64_t *data, MemTxAttrs attrs)\n {\n@@ -325,6 +343,26 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,\n case A_IRS_AIDR:\n *data = cs->irs_aidr;\n return true;\n+\n+ case A_IRS_IST_BASER:\n+ *data = extract64(cs->irs_ist_baser[domain], 0, 32);\n+ return true;\n+\n+ case A_IRS_IST_BASER + 4:\n+ *data = extract64(cs->irs_ist_baser[domain], 32, 32);\n+ return true;\n+\n+ case A_IRS_IST_STATUSR:\n+ /*\n+ * For QEMU writes to IRS_IST_BASER and IRS_MAP_L2_ISTR take effect\n+ * instantaneously, and the guest can never see the IDLE bit as 0.\n+ */\n+ *data = R_IRS_IST_STATUSR_IDLE_MASK;\n+ return true;\n+\n+ case A_IRS_IST_CFGR:\n+ *data = cs->irs_ist_cfgr[domain];\n+ return true;\n }\n \n return false;\n@@ -333,18 +371,54 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,\n static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset,\n uint64_t data, MemTxAttrs attrs)\n {\n+ GICv5Common *cs = ARM_GICV5_COMMON(s);\n+\n+ switch (offset) {\n+ case A_IRS_IST_BASER:\n+ irs_ist_baser_write(s, domain,\n+ deposit64(cs->irs_ist_baser[domain], 0, 32, data));\n+ return true;\n+ case A_IRS_IST_BASER + 4:\n+ irs_ist_baser_write(s, domain,\n+ deposit64(cs->irs_ist_baser[domain], 32, 32, data));\n+ return true;\n+ case A_IRS_IST_CFGR:\n+ if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"guest tried to write IRS_IST_CFGR for %s config frame \"\n+ \"while IST_BASER.VALID set\\n\", domain_name[domain]);\n+ } else {\n+ cs->irs_ist_cfgr[domain] = data;\n+ }\n+ return true;\n+ }\n+\n return false;\n }\n \n static bool config_readll(GICv5 *s, GICv5Domain domain, hwaddr offset,\n uint64_t *data, MemTxAttrs attrs)\n {\n+ GICv5Common *cs = ARM_GICV5_COMMON(s);\n+\n+ switch (offset) {\n+ case A_IRS_IST_BASER:\n+ *data = cs->irs_ist_baser[domain];\n+ return true;\n+ }\n+\n return false;\n }\n \n static bool config_writell(GICv5 *s, GICv5Domain domain, hwaddr offset,\n uint64_t data, MemTxAttrs attrs)\n {\n+ switch (offset) {\n+ case A_IRS_IST_BASER:\n+ irs_ist_baser_write(s, domain, data);\n+ return true;\n+ }\n+\n return false;\n }\n \ndiff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c\nindex 54d75db014..44909d1b05 100644\n--- a/hw/intc/arm_gicv5_common.c\n+++ b/hw/intc/arm_gicv5_common.c\n@@ -62,6 +62,10 @@ void gicv5_common_init_irqs_and_mmio(GICv5Common *cs,\n \n static void gicv5_common_reset_hold(Object *obj, ResetType type)\n {\n+ GICv5Common *cs = ARM_GICV5_COMMON(obj);\n+\n+ memset(cs->irs_ist_baser, 0, sizeof(cs->irs_ist_baser));\n+ memset(cs->irs_ist_cfgr, 0, sizeof(cs->irs_ist_cfgr));\n }\n \n static void gicv5_common_init(Object *obj)\ndiff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5_common.h\nindex 88e1b4d73d..9bfafcebfc 100644\n--- a/include/hw/intc/arm_gicv5_common.h\n+++ b/include/hw/intc/arm_gicv5_common.h\n@@ -62,6 +62,9 @@ struct GICv5Common {\n \n MemoryRegion iomem[NUM_GICV5_DOMAINS];\n \n+ uint64_t irs_ist_baser[NUM_GICV5_DOMAINS];\n+ uint32_t irs_ist_cfgr[NUM_GICV5_DOMAINS];\n+\n /* Bits here are set for each physical interrupt domain implemented */\n uint8_t implemented_domains;\n \n", "prefixes": [ "v2", "16/65" ] }