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GET /api/patches/2216889/?format=api
{ "id": 2216889, "url": "http://patchwork.ozlabs.org/api/patches/2216889/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-38-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-38-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:32", "name": "[v2,37/65] target/arm: GICv5 cpuif: Implement PPI handling mode register", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a0c0e3b0cd0f3b39ccc5093f54e004fe41f6e5d4", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-38-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216889/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216889/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=gUdcvKvX;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyr220cdz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:20:50 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65CB-0006zt-D8; Fri, 27 Mar 2026 07:17:43 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C9-0006vn-0l\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:41 -0400", "from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C7-0008Ca-6j\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:40 -0400", "by mail-wm1-x32b.google.com with SMTP id\n 5b1f17b1804b1-4852a9c6309so17943745e9.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:38 -0700 (PDT)", "from lanath.. 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helo=mail-wm1-x32b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "In the GICv5 the handling mode of a PPI is not software configurable;\nit is reported via read-only CPU interface registers ICC_PPI_HMR0_EL1\nand ICC_PPI_HMR1_EL1.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/cpu.h | 1 +\n target/arm/tcg/gicv5-cpuif.c | 22 ++++++++++++++++++++++\n 2 files changed, 23 insertions(+)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex dd4dc12feb..4574f7005d 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -605,6 +605,7 @@ typedef struct CPUArchState {\n uint64_t icc_icsr_el1;\n /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register */\n uint64_t ppi_active[GICV5_NUM_PPIS / 64];\n+ uint64_t ppi_hm[GICV5_NUM_PPIS / 64];\n } gicv5_cpuif;\n \n struct {\ndiff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 6672cda37f..e65bd56b3d 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -50,6 +50,16 @@ FIELD(ICC_IDR0_EL1, GCIE_LEGACY, 8, 4)\n ((4 << R_ICC_IDR0_EL1_PRI_BITS_SHIFT) | \\\n (1 << R_ICC_IDR0_EL1_ID_BITS_SHIFT))\n \n+/*\n+ * PPI handling modes are fixed and not software configurable.\n+ * R_CFSKX defines them for the architected PPIs: they are all Level,\n+ * except that PPI 24 (CTIIRQ) is IMPDEF and PPI 3 (SW_PPI) is Edge.\n+ * For unimplemented PPIs the field is RES0. The PPI register bits\n+ * are 1 for Level and 0 for Edge.\n+ */\n+#define PPI_HMR0_RESET (~(1ULL << GICV5_PPI_SW_PPI))\n+#define PPI_HMR1_RESET (~0ULL)\n+\n static GICv5Common *gicv5_get_gic(CPUARMState *env)\n {\n return env->gicv5state;\n@@ -292,6 +302,18 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[1]),\n .writefn = gic_ppi_sactive_write,\n },\n+ { .name = \"ICC_PPI_HMR0_EL1\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 0,\n+ .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_hm[0]),\n+ .resetvalue = PPI_HMR0_RESET,\n+ },\n+ { .name = \"ICC_PPI_HMR1_EL1\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 1,\n+ .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]),\n+ .resetvalue = PPI_HMR1_RESET,\n+ },\n };\n \n void define_gicv5_cpuif_regs(ARMCPU *cpu)\n", "prefixes": [ "v2", "37/65" ] }