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GET /api/patches/2216909/?format=api
{ "id": 2216909, "url": "http://patchwork.ozlabs.org/api/patches/2216909/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-54-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-54-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:48", "name": "[v2,53/65] target/arm: Connect internal interrupt sources up as GICv5 PPIs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7017b40c7ed1ba004214e09e5fb0a3da0a2def2a", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-54-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216909/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216909/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=rqI5P0s1;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyv95vMHz1yFr\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:23:33 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Di-00012B-W8; Fri, 27 Mar 2026 07:19:19 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CP-0007G7-JT\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:59 -0400", "from mail-wr1-x432.google.com ([2a00:1450:4864:20::432])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CM-0008Td-VL\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:56 -0400", "by mail-wr1-x432.google.com with SMTP id\n ffacd0b85a97d-43b3d9d0695so1384636f8f.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:53 -0700 (PDT)", "from lanath.. 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[81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.51\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 27 Mar 2026 04:17:51 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1774610272; x=1775215072; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=vYFn49wK2CtOBKQI7tWyVSTEU2OnE1N9jg68K1dqW5o=;\n b=rqI5P0s1z3cQeV2g7BOrZCj33yT288ryAggrXkXuWhcJq1HIZcn/jelxXw2lam07uZ\n NyHEonKovebyYhEc+tDVvwSf1HAeh+6S9uQm4sV15lA7C9KvFdxqzQvH4Z5y2u1S52Lk\n gFbjswoVUJJjfOWQxYxMRI1PK0ypcv84+jFxRypIXyedXEbC0w2G2FjaUiOxSDKU2f2o\n mv4P4jjOJecw0FdVYyEVOuIn4v3syb6RruEjWNSbBYxyw9qFROYNCebqPADxlWZW8NUw\n YHpV3xZGHwU/Z1+bckGaBoEFipOwLax+DSO2qLhZlMIU2KR/eyQdifQl7bF8CRtPp1AU\n xRvg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774610272; x=1775215072;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=vYFn49wK2CtOBKQI7tWyVSTEU2OnE1N9jg68K1dqW5o=;\n b=QqE03u7u2ZhT2AnwvItX9eiYg5NsukPdGiTuQWqStbTchHhyta6CeCEs+0cGVax1yX\n eGZkjYRgB7kHiXBoOxNCxi+u4u7mvGIyIyf35+xEGOcM92DiJukX1MX1A4UKbD3JRbyI\n du0ZeRnfTFUgnq3WvHhgDzRPDNtI0MhBblR3lnHcPuYDf35nNXtUrKQbiydaoY60WfGy\n hUu7t+5yqqrOE1whE9M/3rUmToXev4a6GTpRjqxHilNiP5/HoJ6Yb71cREt7NRIguguN\n q6Pv7PgBAf2TRsl+jSbtwI5D06rB5PV5dJn7Ql52SDjr8JSdHrbvGDnJf4FxryT/7zoG\n XVkQ==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCWnQSb3XpzcjYck2qqFipdhLj/5kNZxr/sm3BKIoMh4D/T97HNHNpsA7DvBWSaFNNVUrIXVaoAZRuju@nongnu.org", "X-Gm-Message-State": "AOJu0Yzui/MP47IlhSt6MHkA/xeapBzBZDV5yRk9xTZqdGNJ/jQ69VwD\n 7V8PvgxtX7r/A+Fgo4OOiM64D1vDjbOpXYpvs5ANJCZjbgvGi0FjsMpeIqXXWgzq/NA=", "X-Gm-Gg": "ATEYQzwJrtDXQD6nNycOHuul2WILXgd7rZwTXpujz97d2enCOF8zahP8Tia6+6XafDM\n G66Plp6yF4RdX/nidyfsJgPpl+SjA5hbOJoDZVT0WD8mByTuGABv/IBPctQuCePMV7vytpB6jce\n uOvWknRWOuX+SBb1AVJhibSR5jawELqOTtAjJELFC+U1u9wZ7JYA/UdoqzA/4ikXY4yp0A3W11O\n lENQdpJHo7gozf+FriiH+fjcJOJDbkE7mW6Fzim2fVbV/ZLjnBQWizSwDcunz+0d5MsJ+WBhYHl\n z2CZILOxenzVCuTou9ViX/xWbCb78dLbY8BrCoeVCFaRkSmy1uKMD30E0K+HmebWNwHokYv96ng\n 8DAlyTBmnxTo1dRlsbBEV5zDxBaxUUxzyCcJR/MJGG1pPMm1zGpTF0ay3eIr/8u5UfZGYzZv0Qo\n AUmNxva9i97zDW9BBWv6ckI9wj+BUiYe04fqKZEn8qTMNiJPLKLlgI5R7gXPIVbjZawMIRe02hP\n EXAa1ov2YYDPsTFvyxMl9MtQrw62z4=", "X-Received": "by 2002:a05:6000:2088:b0:43b:90ab:d326 with SMTP id\n ffacd0b85a97d-43b9eb27225mr3124227f8f.20.1774610272320;\n Fri, 27 Mar 2026 04:17:52 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Jonathan Cameron <jonathan.cameron@huawei.com>", "Subject": "[PATCH v2 53/65] target/arm: Connect internal interrupt sources up as\n GICv5 PPIs", "Date": "Fri, 27 Mar 2026 11:16:48 +0000", "Message-ID": "<20260327111700.795099-54-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327111700.795099-1-peter.maydell@linaro.org>", "References": "<20260327111700.795099-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::432;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The CPU has several interrupt sources which are exposed as GICv5\nPPIs. For QEMU, this means the generic timers and the PMU.\n\nIn GICv3, we implemented these as qemu_irq lines which connect up to\nthe external interrupt controller device. In a GICv5, the PPIs are\nhandled entirely inside the CPU interface, so there are no external\nsignals. Instead we provide a gicv5_update_ppi_state() function\nwhich the emulated timer and PMU code uses to tell the CPU interface\nabout the new state of the PPI source.\n\nWe make the GICv5 function a no-op if there is no GICv5 present, so\nthat calling code can do both \"update the old irq lines\" and \"update\nthe GICv5 PPI\" without having to add conditionals. (In a GICv5\nsystem the old irq lines won't be connected to anything, so the\nqemu_set_irq() will be a no-op.)\n\nUpdating PPIs via either mechanism is unnecessary in user-only mode;\nwe got away with not ifdeffing this away before because\nqemu_set_irq() is built for user-only mode, but since the GICv5 cpuif\ncode is system-emulation only, we do need an ifdef now.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/cpregs-pmu.c | 9 +++++++--\n target/arm/helper.c | 20 ++++++++++++++++++++\n target/arm/internals.h | 6 ++++++\n target/arm/tcg/gicv5-cpuif.c | 28 ++++++++++++++++++++++++++++\n target/arm/tcg/trace-events | 1 +\n 5 files changed, 62 insertions(+), 2 deletions(-)", "diff": "diff --git a/target/arm/cpregs-pmu.c b/target/arm/cpregs-pmu.c\nindex 47e1e4652b..46df6597b1 100644\n--- a/target/arm/cpregs-pmu.c\n+++ b/target/arm/cpregs-pmu.c\n@@ -428,9 +428,14 @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)\n \n static void pmu_update_irq(CPUARMState *env)\n {\n+#ifndef CONFIG_USER_ONLY\n ARMCPU *cpu = env_archcpu(env);\n- qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) &&\n- (env->cp15.c9_pminten & env->cp15.c9_pmovsr));\n+ bool level = (env->cp15.c9_pmcr & PMCRE) &&\n+ (env->cp15.c9_pminten & env->cp15.c9_pmovsr);\n+\n+ gicv5_update_ppi_state(env, GICV5_PPI_PMUIRQ, level);\n+ qemu_set_irq(cpu->pmu_interrupt, level);\n+#endif\n }\n \n static bool pmccntr_clockdiv_enabled(CPUARMState *env)\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 8faca360fc..488a91799e 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -1343,6 +1343,21 @@ uint64_t gt_get_countervalue(CPUARMState *env)\n return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu);\n }\n \n+static void gt_update_gicv5_ppi(CPUARMState *env, int timeridx, bool level)\n+{\n+ static int timeridx_to_ppi[] = {\n+ [GTIMER_PHYS] = GICV5_PPI_CNTP,\n+ [GTIMER_VIRT] = GICV5_PPI_CNTV,\n+ [GTIMER_HYP] = GICV5_PPI_CNTHP,\n+ [GTIMER_SEC] = GICV5_PPI_CNTPS,\n+ [GTIMER_HYPVIRT] = GICV5_PPI_CNTHV,\n+ [GTIMER_S_EL2_PHYS] = GICV5_PPI_CNTHPS,\n+ [GTIMER_S_EL2_VIRT] = GICV5_PPI_CNTHVS,\n+ };\n+\n+ gicv5_update_ppi_state(env, timeridx_to_ppi[timeridx], level);\n+}\n+\n static void gt_update_irq(ARMCPU *cpu, int timeridx)\n {\n CPUARMState *env = &cpu->env;\n@@ -1361,6 +1376,11 @@ static void gt_update_irq(ARMCPU *cpu, int timeridx)\n irqstate = 0;\n }\n \n+ /*\n+ * We update both the GICv5 PPI and the external-GIC irq line\n+ * (whichever of the two mechanisms is unused will do nothing)\n+ */\n+ gt_update_gicv5_ppi(env, timeridx, irqstate);\n qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);\n trace_arm_gt_update_irq(timeridx, irqstate);\n }\ndiff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 9bde58cf00..afe893f49d 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -1800,6 +1800,12 @@ void define_gcs_cpregs(ARMCPU *cpu);\n /* Add the cpreg definitions for the GICv5 CPU interface */\n void define_gicv5_cpuif_regs(ARMCPU *cpu);\n \n+/*\n+ * Update the state of the given GICv5 PPI for this CPU. Does nothing\n+ * if the GICv5 is not present.\n+ */\n+void gicv5_update_ppi_state(CPUARMState *env, int ppi, bool level);\n+\n /* Effective value of MDCR_EL2 */\n static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)\n {\ndiff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 7caf2102a9..44b52a4013 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -309,6 +309,34 @@ void gicv5_forward_interrupt(ARMCPU *cpu, GICv5Domain domain)\n gicv5_update_irq_fiq(&cpu->env);\n }\n \n+void gicv5_update_ppi_state(CPUARMState *env, int ppi, bool level)\n+{\n+ /*\n+ * Update the state of the given PPI (which is connected to some\n+ * CPU-internal source of interrupts, like the timers). We can\n+ * assume that the PPI is fixed as level-triggered, which means\n+ * that its pending state exactly tracks the input (and the guest\n+ * cannot separately change the pending state, because the pending\n+ * bits are RO).\n+ */\n+ int oldlevel;\n+\n+ if (!cpu_isar_feature(aa64_gcie, env_archcpu(env))) {\n+ return;\n+ }\n+\n+ /* The architected PPIs are 0..63, so in the first PPI register. */\n+ assert(ppi >= 0 && ppi < 64);\n+ oldlevel = extract64(env->gicv5_cpuif.ppi_pend[0], ppi, 1);\n+ if (oldlevel != level) {\n+ trace_gicv5_update_ppi_state(ppi, level);\n+\n+ env->gicv5_cpuif.ppi_pend[0] =\n+ deposit64(env->gicv5_cpuif.ppi_pend[0], ppi, 1, level);\n+ gic_recalc_ppi_hppi(env);\n+ }\n+}\n+\n static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri,\n uint64_t value)\n {\ndiff --git a/target/arm/tcg/trace-events b/target/arm/tcg/trace-events\nindex 2bfa8fc552..bf1803c872 100644\n--- a/target/arm/tcg/trace-events\n+++ b/target/arm/tcg/trace-events\n@@ -8,3 +8,4 @@ gicv5_gicr_cdia(int domain, uint32_t id) \"domain %d CDIA acknowledge of interrup\n gicv5_cdeoi(int domain) \"domain %d CDEOI performing priority drop\"\n gicv5_cddi(int domain, uint32_t id) \"domain %d CDDI deactivating interrupt ID 0x%x\"\n gicv5_update_irq_fiq(bool irq, bool fiq, bool nmi) \"now IRQ %d FIQ %d NMI %d\"\n+gicv5_update_ppi_state(int ppi, bool level) \"PPI %d source level now %d\"\n", "prefixes": [ "v2", "53/65" ] }