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GET /api/patches/2216895/?format=api
{ "id": 2216895, "url": "http://patchwork.ozlabs.org/api/patches/2216895/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-16-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-16-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:10", "name": "[v2,15/65] target/arm: Set up pointer to GICv5 in each CPU", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1eff95e390a8ea1f6080af780434e0c3235d407c", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-16-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216895/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216895/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=AdgUgXPY;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhys72PVWz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:21:47 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Bq-0006Uj-Cs; Fri, 27 Mar 2026 07:17:22 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bo-0006T1-Mv\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:20 -0400", "from mail-wr1-x429.google.com ([2a00:1450:4864:20::429])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bm-0007tW-9N\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:20 -0400", "by mail-wr1-x429.google.com with SMTP id\n ffacd0b85a97d-43b87970468so1944320f8f.3\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:17 -0700 (PDT)", "from lanath.. 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Set this up in a similar way to how we\ndo it for the GICv3: have the GIC's realize function call\ngicv5_set_gicv5state() to set a pointer in the CPUARMState.\n\nThe CPU will only allow this link to be made if it actually\nimplements the GICv5 CPU interface; it will be the responsibility of\nthe board code to configure the CPU to have a GICv5 cpuif if it wants\nto connect a GICv5 to it.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5_common.c | 9 +++++++++\n include/hw/intc/arm_gicv5_stream.h | 32 ++++++++++++++++++++++++++++++\n target/arm/cpu.c | 16 +++++++++++++++\n target/arm/cpu.h | 2 ++\n 4 files changed, 59 insertions(+)\n create mode 100644 include/hw/intc/arm_gicv5_stream.h", "diff": "diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c\nindex 7f15e3c7c8..54d75db014 100644\n--- a/hw/intc/arm_gicv5_common.c\n+++ b/hw/intc/arm_gicv5_common.c\n@@ -8,6 +8,7 @@\n \n #include \"qemu/osdep.h\"\n #include \"hw/intc/arm_gicv5_common.h\"\n+#include \"hw/intc/arm_gicv5_stream.h\"\n #include \"hw/core/qdev-properties.h\"\n #include \"qapi/error.h\"\n #include \"trace.h\"\n@@ -129,6 +130,14 @@ static void gicv5_common_realize(DeviceState *dev, Error **errp)\n return;\n }\n \n+ for (int i = 0; i < cs->num_cpus; i++) {\n+ if (!gicv5_set_gicv5state(cs->cpus[i], cs)) {\n+ error_setg(errp,\n+ \"CPU %d does not implement GICv5 CPU interface\", i);\n+ return;\n+ }\n+ }\n+\n address_space_init(&cs->dma_as, cs->dma, \"gicv5-sysmem\");\n \n trace_gicv5_common_realize(cs->irsid, cs->num_cpus,\ndiff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5_stream.h\nnew file mode 100644\nindex 0000000000..7257ddde90\n--- /dev/null\n+++ b/include/hw/intc/arm_gicv5_stream.h\n@@ -0,0 +1,32 @@\n+/*\n+ * Interface between GICv5 CPU interface and GICv5 IRS\n+ * Loosely modelled on the GICv5 Stream Protocol interface documented\n+ * in the GICv5 specification.\n+ *\n+ * Copyright (c) 2025 Linaro Limited\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HW_INTC_ARM_GICV5_STREAM_H\n+#define HW_INTC_ARM_GICV5_STREAM_H\n+\n+#include \"target/arm/cpu-qom.h\"\n+\n+typedef struct GICv5Common GICv5Common;\n+\n+/**\n+ * gicv5_set_gicv5state\n+ * @cpu: CPU object to tell about its IRS\n+ * @cs: the GIC IRS it is connected to\n+ *\n+ * Set the CPU object's GICv5 pointer to point to this GIC IRS. The\n+ * IRS must call this when it is realized, for each CPU it is\n+ * connected to.\n+ *\n+ * Returns true on success, false if the CPU doesn't implement the\n+ * GICv5 CPU interface.\n+ */\n+bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs);\n+\n+#endif\ndiff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex ccc47c8a9a..4044bce5b6 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -41,6 +41,7 @@\n #include \"hw/core/boards.h\"\n #ifdef CONFIG_TCG\n #include \"hw/intc/armv7m_nvic.h\"\n+#include \"hw/intc/arm_gicv5_stream.h\"\n #endif /* CONFIG_TCG */\n #endif /* !CONFIG_USER_ONLY */\n #include \"system/tcg.h\"\n@@ -1085,6 +1086,21 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)\n }\n }\n \n+#ifndef CONFIG_USER_ONLY\n+bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs)\n+{\n+ /*\n+ * Set this CPU's gicv5state pointer to point to the GIC that we are\n+ * connected to.\n+ */\n+ if (!cpu_isar_feature(aa64_gcie, cpu)) {\n+ return false;\n+ }\n+ cpu->env.gicv5state = cs;\n+ return true;\n+}\n+#endif\n+\n uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz)\n {\n uint32_t Aff1 = idx / clustersz;\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 657ff4ab20..16de0ebfa8 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -812,6 +812,8 @@ typedef struct CPUArchState {\n const struct arm_boot_info *boot_info;\n /* Store GICv3CPUState to access from this struct */\n void *gicv3state;\n+ /* Similarly, for a GICv5Common */\n+ void *gicv5state;\n #else /* CONFIG_USER_ONLY */\n /* For usermode syscall translation. */\n bool eabi;\n", "prefixes": [ "v2", "15/65" ] }