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GET /api/patches/2216890/?format=api
{ "id": 2216890, "url": "http://patchwork.ozlabs.org/api/patches/2216890/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-33-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-33-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:27", "name": "[v2,32/65] hw/intc/arm_gicv5: Implement CoreSight ID registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b2b50ed5fe729f2a4dc3fe06addcde8ef7bc13be", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-33-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216890/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216890/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=adxYthpy;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyrC0STzz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:20:59 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65C6-0006rC-4a; Fri, 27 Mar 2026 07:17:38 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C3-0006o4-L2\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:35 -0400", "from mail-wr1-x432.google.com ([2a00:1450:4864:20::432])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C1-00083m-W9\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:35 -0400", "by mail-wr1-x432.google.com with SMTP id\n ffacd0b85a97d-43b3d9d0695so1384403f8f.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:33 -0700 (PDT)", "from lanath.. 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Although we only have one\ncallsite at the moment, the ITS config frame uses the same ID\nregister values, so we abstract this out into a function we can reuse\nlater.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/intc/arm_gicv5.c | 35 +++++++++++++++++++++++++++++++++++\n 1 file changed, 35 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex a95a9dc16b..866c1333c3 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -285,6 +285,9 @@ REG64(IRS_SWERR_SYNDROMER0, 0x3c8)\n REG64(IRS_SWERR_SYNDROMER1, 0x3d0)\n FIELD(IRS_SWERR_SYNDROMER2, ADDR, 3, 53)\n \n+REG32(IRS_IDREGS, 0xffd0)\n+REG32(IRS_DEVARCH, 0xffbc)\n+\n FIELD(L1_ISTE, VALID, 0, 1)\n FIELD(L1_ISTE, L2_ADDR, 12, 44)\n \n@@ -310,6 +313,31 @@ FIELD(ICSR, HM, 5, 1)\n FIELD(ICSR, PRIORITY, 11, 5)\n FIELD(ICSR, IAFFID, 32, 16)\n \n+#define IRS_DEVARCH_VALUE ((0x23b << 31) | (0x1 << 20) | 0x5a19)\n+\n+static uint32_t gicv5_idreg(int regoffset)\n+{\n+ /*\n+ * As with the main IRS_IIDR, we don't identify as a specific\n+ * hardware GICv5 implementation. Arm suggests that the\n+ * Implementer, Product, etc in IRS_IIDR should also be reported\n+ * here, so we do that.\n+ */\n+ static const uint8_t gic_ids[] = {\n+ QEMU_GICV5_IMPLEMENTER >> 8, 0x00, 0x00, 0x00, /* PIDR4..PIDR7 */\n+ QEMU_GICV5_PRODUCTID & 0xff, /* PIDR0 */\n+ ((QEMU_GICV5_PRODUCTID >> 8) |\n+ ((QEMU_GICV5_IMPLEMENTER & 0xf) << 4)), /* PIDR1 */\n+ ((QEMU_GICV5_REVISION << 4) | (1 << 3) |\n+ ((QEMU_GICV5_IMPLEMENTER & 0x70) >> 4)), /* PIDR2 */\n+ QEMU_GICV5_VARIANT << 4, /* PIDR3 */\n+ 0x0D, 0xF0, 0x05, 0xB1, /* CIDR0..CIDR3 */\n+ };\n+\n+ regoffset /= 4;\n+ return gic_ids[regoffset];\n+}\n+\n static GICv5SPIState *spi_for_selr(GICv5Common *cs, GICv5Domain domain)\n {\n /*\n@@ -1124,6 +1152,13 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,\n }\n *data = v;\n return true;\n+ case A_IRS_DEVARCH:\n+ *data = IRS_DEVARCH_VALUE;\n+ return true;\n+ case A_IRS_IDREGS ... A_IRS_IDREGS + 0x2f:\n+ /* CoreSight ID registers */\n+ *data = gicv5_idreg(offset - A_IRS_IDREGS);\n+ return true;\n }\n \n return false;\n", "prefixes": [ "v2", "32/65" ] }