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GET /api/patches/2216883/?format=api
{ "id": 2216883, "url": "http://patchwork.ozlabs.org/api/patches/2216883/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-24-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-24-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:18", "name": "[v2,23/65] hw/intc/arm_gicv5: Create backing state for SPIs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e685566d399aed4f9e2c6e8b9c190cf8dec4b5f9", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-24-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216883/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216883/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=gJfd9yUp;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhypv6Q9xz1y1x\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:19:51 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65C3-0006md-0d; Fri, 27 Mar 2026 07:17:35 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bv-0006cc-Ty\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:27 -0400", "from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bt-0007xL-Kd\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:27 -0400", "by mail-wm1-x32a.google.com with SMTP id\n 5b1f17b1804b1-486fe655187so22895795e9.2\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:25 -0700 (PDT)", "from lanath.. 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For QEMU we want to use\nthese for all our traditional fixed-wire interrupt devices. (The\nother option the architecture permits is an Interrupt Wire Bridge\n(IWB), which converts from a fixed-wire interrupt to an interrupt\nevent that is then translated through an ITS to send an LPI to the\nITS -- this is much more complexity than we need or want.)\n\nSPI configuration is set via the same CPUIF instructions as LPI\nconfiguration. Create an array of structs which track the SPI state\ninformation listed in I_JVVTZ and I_BWPPP (ignoring for the moment\nthe VM assignment state, which we will add when we add virtualization\nsupport).\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5_common.c | 30 ++++++++++++++++++++++++++++++\n include/hw/intc/arm_gicv5_common.h | 27 +++++++++++++++++++++++++++\n include/hw/intc/arm_gicv5_types.h | 14 ++++++++++++++\n 3 files changed, 71 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c\nindex 44909d1b05..79876c4401 100644\n--- a/hw/intc/arm_gicv5_common.c\n+++ b/hw/intc/arm_gicv5_common.c\n@@ -66,6 +66,34 @@ static void gicv5_common_reset_hold(Object *obj, ResetType type)\n \n memset(cs->irs_ist_baser, 0, sizeof(cs->irs_ist_baser));\n memset(cs->irs_ist_cfgr, 0, sizeof(cs->irs_ist_cfgr));\n+\n+ if (cs->spi) {\n+ GICv5Domain mp_domain;\n+\n+ /*\n+ * D_YGLYC, D_TVVRZ: SPIs reset to edge-triggered, inactive,\n+ * idle, disabled, targeted routing mode, not assigned to a\n+ * VM, and assigned to the most-privileged interrupt domain.\n+ * Other state is UNKNOWN: we choose to zero it.\n+ */\n+ memset(cs->spi, 0, cs->spi_irs_range * sizeof(*cs->spi));\n+\n+ /*\n+ * The most-privileged interrupt domain is effectively the\n+ * first in the list (EL3, S, NS) that we implement.\n+ */\n+ if (gicv5_domain_implemented(cs, GICV5_ID_EL3)) {\n+ mp_domain = GICV5_ID_EL3;\n+ } else if (gicv5_domain_implemented(cs, GICV5_ID_S)) {\n+ mp_domain = GICV5_ID_S;\n+ } else {\n+ mp_domain = GICV5_ID_NS;\n+ }\n+\n+ for (int i = 0; i < cs->spi_irs_range; i++) {\n+ cs->spi[i].domain = mp_domain;\n+ }\n+ }\n }\n \n static void gicv5_common_init(Object *obj)\n@@ -144,6 +172,8 @@ static void gicv5_common_realize(DeviceState *dev, Error **errp)\n \n address_space_init(&cs->dma_as, cs->dma, \"gicv5-sysmem\");\n \n+ cs->spi = g_new0(GICv5SPIState, cs->spi_irs_range);\n+\n trace_gicv5_common_realize(cs->irsid, cs->num_cpus,\n cs->spi_base, cs->spi_irs_range, cs->spi_range);\n }\ndiff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5_common.h\nindex 9bfafcebfc..d3f4999321 100644\n--- a/include/hw/intc/arm_gicv5_common.h\n+++ b/include/hw/intc/arm_gicv5_common.h\n@@ -53,6 +53,25 @@\n \n OBJECT_DECLARE_TYPE(GICv5Common, GICv5CommonClass, ARM_GICV5_COMMON)\n \n+/*\n+ * This is where we store the state the IRS handles for an SPI.\n+ * Generally this corresponds to the spec's list of state in I_JVVTZ\n+ * and J_BWPPP. level is a QEMU implementation detail and is where we\n+ * store the actual current state of the incoming qemu_irq line.\n+ */\n+typedef struct GICv5SPIState {\n+ uint32_t iaffid;\n+ uint8_t priority;\n+ bool level;\n+ bool pending;\n+ bool active;\n+ bool enabled;\n+ GICv5HandlingMode hm;\n+ GICv5RoutingMode irm;\n+ GICv5TriggerMode tm;\n+ GICv5Domain domain;\n+} GICv5SPIState;\n+\n /*\n * This class is for common state that will eventually be shared\n * between TCG and KVM implementations of the GICv5.\n@@ -65,6 +84,14 @@ struct GICv5Common {\n uint64_t irs_ist_baser[NUM_GICV5_DOMAINS];\n uint32_t irs_ist_cfgr[NUM_GICV5_DOMAINS];\n \n+ /*\n+ * Pointer to an array of state information for the SPIs. Array\n+ * element 0 is SPI ID s->spi_base, and there are s->spi_irs_range\n+ * elements in total. SPI state is not per-domain: SPI is\n+ * configurable to a particular domain via IRS_SPI_DOMAINR.\n+ */\n+ GICv5SPIState *spi;\n+\n /* Bits here are set for each physical interrupt domain implemented */\n uint8_t implemented_domains;\n \ndiff --git a/include/hw/intc/arm_gicv5_types.h b/include/hw/intc/arm_gicv5_types.h\nindex 20de5b3f46..f6f8709a6a 100644\n--- a/include/hw/intc/arm_gicv5_types.h\n+++ b/include/hw/intc/arm_gicv5_types.h\n@@ -70,4 +70,18 @@ typedef enum GICv5RoutingMode {\n GICV5_1OFN = 1,\n } GICv5RoutingMode;\n \n+/*\n+ * Interrupt trigger mode (same encoding as IRS_SPI_CFGR.TM) Note that\n+ * this is not the same thing as handling mode, even though the two\n+ * possible states have the same names. Trigger mode applies only for\n+ * SPIs and tells the IRS what kinds of changes to the input signal\n+ * wire should make it generate SET and CLEAR events. Handling mode\n+ * affects whether the pending state of an interrupt is cleared when\n+ * the interrupt is acknowledged, and applies to both SPIs and LPIs.\n+ */\n+typedef enum GICv5TriggerMode {\n+ GICV5_TRIGGER_EDGE = 0,\n+ GICV5_TRIGGER_LEVEL = 1,\n+} GICv5TriggerMode;\n+\n #endif\n", "prefixes": [ "v2", "23/65" ] }