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{ "id": 2216871, "url": "http://patchwork.ozlabs.org/api/covers/2216871/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260327111700.795099-1-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-1-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:15:55", "name": "[v2,00/65] arm: Implement an emulation of GICv5 interrupt controller", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260327111700.795099-1-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2216871/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=sTzTn0kd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhymf37Cpz1yFx\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:17:54 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Bc-0006LO-Se; Fri, 27 Mar 2026 07:17:08 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Ba-0006K7-FV\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:06 -0400", "from mail-wr1-x432.google.com ([2a00:1450:4864:20::432])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65BX-0007TQ-Te\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:06 -0400", "by mail-wr1-x432.google.com with SMTP id\n ffacd0b85a97d-439bc14dcf4so2270946f8f.1\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:03 -0700 (PDT)", "from lanath.. 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::432;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This patchset implements initial support of emulation of Arm's new\ninterrupt controller architecture, GICv5.\n\nI've incorporated the review feedback from v1, so I figured I\nmight as well send this out, though obviously there's no huge\nrush to review given we're in freeze.\n\nPatches still needing review: 10 24 25 32\n\nChanges v1->v2:\n * minor tidyups to line wrap, etc, in various patches\n * patch 1 is split into 2 patches but otherwise unchanged\n * 3: define FRAME_OP_ENTRY macro to avoid duplication in writing\n out entries of the config_frame_ops[] array\n * 9: fixed IRS_IDR0 PA_RANGE field length\n * 10: also zero IDR0 VIRT_ONE_N field for the EL3 domain\n * 18, 21, 24, 25, 47, 50: use switch on IRQ type instead of if()\n in gicv5_set_priority() and similar functions\n * old 55 (\"hw/arm/virt: Update error message for bad gic-version\n option\") is now upstream, so dropped from v2\n\n\n(Everything below here is the same as from v1's cover letter;\nrepeated for context.)\n\nThe most recent version of the GICv5 spec (currently 00EAC0) is at:\nhttps://developer.arm.com/documentation/aes0070/latest/\n\nThe emulation is at an \"experimental\" level, both because the GICv5\nspecification is still at an early-access level and minor changes are\npossible, and also because this emulation is missing some\nfunctionality which I plan to add later but which would have made this\ninitial patchset even larger and later. To quote the docs patch:\n\n - guest-visible behaviour may change when the final version of\n the specification is released and QEMU implements it\n - migration support is not yet implemented\n - the GICv5 is not exposed to the guest via ACPI tables, only via DTB\n - the way the interrupt controller is exposed to the guest and the\n command line syntax for enabling it may change\n\n The current implementation supports only an EL1 guest (no EL2 or\n EL3 and no Realm support), and does not implement the ITS (no\n MSI support).\n\nThe GICv5 is supported by the \"virt\" board, and can be enabled with\n\"-machine gic-version=x-5\" (the 'x' standing for \"experimental\").\n\nLike the GICv3/v4, the GICv5 has both a system component part (the\nInterrupt Routing Service, IRS), and a part in the CPU itself (the CPU\ninterface). Our GICv3 model puts both of these into code in hw/intc/,\nand has the cpuif part install itself into an existing CPU object by\nadding new system registers there. This works, but in retrospect I\nfeel that it's a bit awkward and we would have done better to make our\ndesign a bit closer to the hardware setup, where the CPU interface is\nreally part of the CPU and talks to the system component over an\narchitected protocol. So for GICv5 I have taken that route: the IRS is\nin hw/intc/arm_gicv5.c, and the CPU interface is in\ntarget/arm/tcg/gicv5-cpuif.c. They communicate via a set of functions\nwhich loosely match the \"stream protocol\" defined in the GICv5\narchitecture spec (with some simplifications that result from QEMU\nbeing strictly synchronous because we always hold the BQL when\nexecuting any GICv5 emulation code; the hardware has to handle the IRS\nand the CPU executing in parallel and the communications channel not\nbeing instantaneous transmission).\n\nAlthough the EL2/EL3/Realm functionality is not present in this\npatchset, I have implemented some of the foundations for it where I\nthought it made sense, to avoid having to refactor it later.\nSimilarly, the class structure makes the usual \"common baseclass + TCG\nsubclass\" split, as we are going to want a KVM subclass when we add\nKVM support.\n\nIn a few places I have noted possible opportunities for performance\noptimisation; these are probably best left until we've done some\nanalysis that shows them to be necessary.\n\nThis patchset is sufficient to be able to boot a Linux guest at EL1\n(directly via -kernel): all the kernel support for GICv5 is upstream\nas of Linux 6.19.\n\nthanks\n-- PMM\n\nPeter Maydell (65):\n qom/object: Add object_resolve_and_typecheck()\n hw/core: Permit devices to define an array of link properties\n hw/intc: Skeleton of GICv5 IRS classes\n hw/arm/Kconfig: select ARM_GICV5 for ARM_VIRT board\n hw/intc/arm_gicv5: Implement skeleton code for IRS register frames\n hw/intc/arm_gicv5: Add migration blocker\n hw/intc/arm_gicv5: Create and validate QOM properties\n hw/intc/arm_gicv5: Create inbound GPIO lines for SPIs\n hw/intc/arm_gicv5: Define macros for config frame registers\n hw/intc/arm_gicv5: Implement IRS ID regs\n hw/intc/arm_gicv5: Add link property for MemoryRegion for DMA\n hw/intc/arm_gicv5: Implement gicv5_class_name()\n hw/intc/arm_gicv5: Add defines for GICv5 architected PPIs\n target/arm: GICv5 cpuif: Initial skeleton and GSB barrier insns\n target/arm: Set up pointer to GICv5 in each CPU\n hw/intc/arm_gicv5: Implement IRS_IST_{BASER, STATUSR, CFGR}\n hw/intc/arm_gicv5: Cache LPI IST config in a struct\n hw/intc/arm_gicv5: Implement gicv5_set_priority()\n target/arm: GICv5 cpuif: Implement the GIC CDPRI instruction\n hw/intc/arm_gicv5: Implement IRS_MAP_L2_ISTR\n hw/intc/arm_gicv5: Implement remaining set-config functions\n target/arm: GICv5 cpuif: Implement GIC CD* insns for setting config\n hw/intc/arm_gicv5: Create backing state for SPIs\n hw/intc/arm_gicv5: Make gicv5_set_* update SPI state\n hw/intc/arm_gicv5: Implement gicv5_request_config()\n target/arm: GICv5 cpuif: Implement GIC CDRCFG and ICC_ICSR_EL1\n hw/intc/arm_gicv5: Implement IRS_SPI_{SELR,STATUSR,CFGR,DOMAINR}\n hw/intc/arm_gicv5: Update SPI state for CLEAR/SET events\n hw/intc/arm_gicv5: Implement IRS_CR0 and IRS_CR1\n hw/intc/arm_gicv5: Implement IRS_SYNCR and IRS_SYNC_STATUSR\n hw/intc/arm_gicv5: Implement IRS_PE_{CR0,SELR,STATUSR}\n hw/intc/arm_gicv5: Implement CoreSight ID registers\n hw/intc/arm_gicv5: Cache pending LPIs in a hash table\n target/arm: GICv5 cpuif: Implement ICC_IAFFIDR_EL1\n target/arm: GICv5 cpuif: Implement ICC_IDR0_EL1\n target/arm: GICv5 cpuif: Implement GICv5 PPI active set/clear\n registers\n target/arm: GICv5 cpuif: Implement PPI handling mode register\n target/arm: GICv5 cpuif: Implement PPI pending status registers\n target/arm: GICv5 cpuif: Implement PPI enable register\n target/arm: GICv5 cpuif: Implement PPI priority registers\n target/arm: GICv5 cpuif: Implement ICC_APR_EL1 and ICC_HAPR_EL1\n target/arm: GICv5 cpuif: Calculate the highest priority PPI\n hw/intc/arm_gicv5: Calculate HPPI in the IRS\n target/arm: GICv5 cpuif: Implement ICC_CR0_EL1\n target/arm: GICv5 cpuif: Implement ICC_PCR_EL1\n target/arm: GICv5 cpuif: Implement ICC_HPPIR_EL1\n hw/intc/arm_gicv5: Implement Activate command\n target/arm: GICv5 cpuif: Implement GICR CDIA command\n target/arm: GICv5 cpuif: Implement GIC CDEOI\n hw/intc/arm_gicv5: Implement Deactivate command\n target/arm: GICv5 cpuif: Implement GIC CDDI\n target/arm: GICv5 cpuif: Signal IRQ or FIQ\n target/arm: Connect internal interrupt sources up as GICv5 PPIs\n target/arm: Add has_gcie property to enable FEAT_GCIE\n hw/intc/arm_gicv3_cpuif: Don't allow GICv3 if CPU has GICv5 cpuif\n hw/arm/virt: Remember CPU phandles rather than looking them up by name\n hw/arm/virt: Move MSI controller creation out of create_gic()\n hw/arm/virt: Pull \"wire CPU interrupts\" out of create_gic()\n hw/arm/virt: Split GICv2 and GICv3/4 creation\n hw/arm/virt: Create and connect GICv5\n hw/arm/virt: Advertise GICv5 in the DTB\n hw/arm/virt: Handle GICv5 in interrupt bindings for PPIs\n hw/arm/virt: Use correct interrupt type for GICv5 SPIs in the DTB\n hw/arm/virt: Enable GICv5 CPU interface when using GICv5\n hw/arm/virt: Allow user to select GICv5\n\n docs/system/arm/virt.rst | 19 +\n hw/arm/Kconfig | 1 +\n hw/arm/virt.c | 525 ++++++--\n hw/core/qdev-properties.c | 78 ++\n hw/intc/Kconfig | 4 +\n hw/intc/arm_gicv3.c | 2 +-\n hw/intc/arm_gicv3_cpuif.c | 14 +-\n hw/intc/arm_gicv5.c | 1962 ++++++++++++++++++++++++++++\n hw/intc/arm_gicv5_common.c | 227 ++++\n hw/intc/gicv3_internal.h | 2 +-\n hw/intc/meson.build | 4 +\n hw/intc/trace-events | 23 +\n include/hw/arm/fdt.h | 10 +\n include/hw/arm/virt.h | 15 +\n include/hw/core/qdev-properties.h | 41 +\n include/hw/intc/arm_gicv5.h | 51 +\n include/hw/intc/arm_gicv5_common.h | 236 ++++\n include/hw/intc/arm_gicv5_stream.h | 228 ++++\n include/hw/intc/arm_gicv5_types.h | 110 ++\n include/qom/object.h | 17 +\n meson.build | 1 +\n qom/object.c | 41 +-\n target/arm/cpregs-pmu.c | 9 +-\n target/arm/cpu-features.h | 11 +\n target/arm/cpu.c | 62 +\n target/arm/cpu.h | 28 +\n target/arm/helper.c | 21 +\n target/arm/internals.h | 9 +\n target/arm/tcg/gicv5-cpuif.c | 952 ++++++++++++++\n target/arm/tcg/meson.build | 1 +\n target/arm/tcg/trace-events | 11 +\n target/arm/tcg/trace.h | 1 +\n 32 files changed, 4559 insertions(+), 157 deletions(-)\n create mode 100644 hw/intc/arm_gicv5.c\n create mode 100644 hw/intc/arm_gicv5_common.c\n create mode 100644 include/hw/intc/arm_gicv5.h\n create mode 100644 include/hw/intc/arm_gicv5_common.h\n create mode 100644 include/hw/intc/arm_gicv5_stream.h\n create mode 100644 include/hw/intc/arm_gicv5_types.h\n create mode 100644 target/arm/tcg/gicv5-cpuif.c\n create mode 100644 target/arm/tcg/trace-events\n create mode 100644 target/arm/tcg/trace.h" }