Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2216933/?format=api
{ "id": 2216933, "url": "http://patchwork.ozlabs.org/api/patches/2216933/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-8-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-8-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:02", "name": "[v2,07/65] hw/intc/arm_gicv5: Create and validate QOM properties", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8ccd8894dbd9c28853168638a8546b3cfd7118a3", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-8-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216933/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216933/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=lEylRPec;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyyn4z4wz1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:26:41 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Br-0006Vv-7s; Fri, 27 Mar 2026 07:17:23 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bg-0006NT-RB\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:13 -0400", "from mail-wr1-x434.google.com ([2a00:1450:4864:20::434])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Be-0007iO-5o\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:12 -0400", "by mail-wr1-x434.google.com with SMTP id\n ffacd0b85a97d-43b9144790dso1094565f8f.1\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:09 -0700 (PDT)", "from lanath.. (wildly.archaic.org.uk. [81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.07\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 27 Mar 2026 04:17:07 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1774610229; x=1775215029; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=q+a1vwfitmUycYoLhCWK2VU83xMZoXvp5UmVsl5NDqE=;\n b=lEylRPecf3ETM0SZpitVH3iRx5+8a0lGeOD2Esb82yb6HuBZZ1l+QYe7JBN91hULEI\n 3HBLmtm/jAHLkxv+ytquagJkohv5z5CSghE0YT7U/prR13ImUxEa70F434OI1wHFjbNI\n jtifb5Dmc5O6B0T8e7rtHH7bDrY7NYTIrTcW7No6mWPCGsZv+PmGzNNUrJGenF7yz8/5\n mE8/kYdxDdNWEwHmt2iU7rXNhaHRchxppViNmZ1pxbFhhtzrWNycOCMwfbx1+IGi5Lom\n jnznG5sCMXNMQKdAHg3TglbVyVDu543At6hCbkMYnHJIZCypnmqerxzszCbGJqVfutYN\n EOdw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774610229; x=1775215029;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=q+a1vwfitmUycYoLhCWK2VU83xMZoXvp5UmVsl5NDqE=;\n b=rDYFyV+IqJhQ1IPR+bMfsE5T7AFBEPKWVw1VafUQj00T3mAz3b0LW5TG9dwHu561Cr\n Riy7Ygkky3MyKPyUaJts2DHWZlAkXem+ASLfVTX1gW5EEQMWUeuckLwsHUXf3+a8Dds2\n JUfobkFTMzoHNBfo826iqdaBj7HqFF/VLlZGy2oGO2t1ijFGK33942l3ZYzEz2yh9VFj\n OMEZZ0vuj4HW4tVcnzovKfBwkiU50ipW0Bo1niH1UH0qvmK3VEN3IIBQwUZWPEcQHhFl\n J2JdSPlECfkai+NkksUrNbqsJoIGMHD+LVMBkFzJMLvyyKEiqMe1NeH7AE1CRduEHS6F\n hyvA==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCWdW2qX3BAREO9k39cjVTqGXqoQsUn/alQdRs1ig3QegOpsldpoK3RZvEgVy+lbvdnKCFirHU9Nmnck@nongnu.org", "X-Gm-Message-State": "AOJu0YxfEOvApBrmG+J5KVxeksDR+ZRPOEGafkkl95i4lQXt/BcW8BD9\n k6YlAVW0SYMns6gkoUEe8n+Sg7XXeCUx8lWRyuhnm/Dxmd1O43i5RytgYgqy70h0iEEt8Szih3k\n HVGCFyno=", "X-Gm-Gg": "ATEYQzxREGyK6hzzppVt2fdMMzBBlc4bBd6fjOMJtX3jkpX8+ymD62OGc4KyS1DJAeS\n c921VoF70LnP3z8D46r9iDZQeXBbdjMXr1r7jHNQUslnVb59FC+vpFCyQj7+KPF+l+KpP2yLnI7\n 7PshchhwBgWCxHMa2BDmR/YFb1HmXGUtWwGWIFk18zcmORny3qIL0mNuCORNeKEZmkOX3It6d4I\n zL23G4Xql1x0QhpUewROjvtIzOwJkHhvDdMqZBpM6wDBWbaZ/WM3b1Jd53XXm1DXEFLjyVzSVDj\n 7SuUJVRF7Bkn30YKDzA/OhVgJfM0u7YMzeqvxmquey2acmaziWXrMN2UEUtAtC38M0bmJUJYorf\n J26gLBsSM/L/Il3IN4ppIq8tpWMlfgU/peGv+uEsrZsVnPUtbj519TcM+4mIWuMJ3MrgRg4SLmA\n YLfO6gNFTvNthcE6Xy6CUdJ9ZToJYp3WmVu67TUCHGRERjZZoqfDwkqUyBVunR2SvZbgB+DZ6Zz\n NCWjcB9p/FDcicnpLZv/9rdi7a9dj0=", "X-Received": "by 2002:a05:6000:613:b0:43b:8766:600b with SMTP id\n ffacd0b85a97d-43b9ea11981mr3393090f8f.49.1774610228476;\n Fri, 27 Mar 2026 04:17:08 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Jonathan Cameron <jonathan.cameron@huawei.com>", "Subject": "[PATCH v2 07/65] hw/intc/arm_gicv5: Create and validate QOM\n properties", "Date": "Fri, 27 Mar 2026 11:16:02 +0000", "Message-ID": "<20260327111700.795099-8-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327111700.795099-1-peter.maydell@linaro.org>", "References": "<20260327111700.795099-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::434;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add code to the GICv5 skeleton which creates the QOM properties which\nthe board or SoC can use to configure the GIC, and the validation\ncode to check they are in range. Generally these correspond to\nfields in the IRS ID registers, and the properties are named\ncorrespondingly.\n\nNotable here is that unlike the GICv3 (which assumes its connected\nCPUs are the system's CPUs starting from 0), we define a QOM array\nproperty which is an array of pointers to the CPUs, and a QOM array\nproperty which is an array of integers telling the GIC what the\nIAFFID (interrupt affinity ID) for each CPU is; so a board or SoC\nwhich wants to connect multiple CPUs to this GICv5 would do something\nlike:\n\n QList *cpulist = qlist_new(), *iaffidlist = qlist_new();\n\n for (int i = 0; i < ms->smp.cpus; i++) {\n qlist_append_link(cpulist, OBJECT(qemu_get_cpu(i)));\n qlist_append_int(iaffidlist, i);\n }\n qdev_prop_set_array(vms->gic, \"cpus\", cpulist);\n qdev_prop_set_array(vms->gic, \"cpu-iaffids\", iaffidlist);\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5_common.c | 80 ++++++++++++++++++++++++++++++\n hw/intc/trace-events | 3 ++\n include/hw/intc/arm_gicv5_common.h | 25 ++++++++++\n 3 files changed, 108 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c\nindex bf990bfa54..3448734686 100644\n--- a/hw/intc/arm_gicv5_common.c\n+++ b/hw/intc/arm_gicv5_common.c\n@@ -8,9 +8,15 @@\n \n #include \"qemu/osdep.h\"\n #include \"hw/intc/arm_gicv5_common.h\"\n+#include \"hw/core/qdev-properties.h\"\n+#include \"qapi/error.h\"\n+#include \"trace.h\"\n \n OBJECT_DEFINE_ABSTRACT_TYPE(GICv5Common, gicv5_common, ARM_GICV5_COMMON, SYS_BUS_DEVICE)\n \n+/* Any value > 2^24 is out of the valid range for this property */\n+#define GICV5_SPI_IRS_RANGE_NOT_SET 0xffffffff\n+\n static bool bad_frame_accepts(void *opaque, hwaddr addr, unsigned size,\n bool is_write, MemTxAttrs attrs)\n {\n@@ -58,9 +64,83 @@ static void gicv5_common_finalize(Object *obj)\n {\n }\n \n+static void gicv5_common_realize(DeviceState *dev, Error **errp)\n+{\n+ GICv5Common *cs = ARM_GICV5_COMMON(dev);\n+\n+ if (cs->num_cpus == 0) {\n+ error_setg(errp, \"The cpus array property must have at least one CPU\");\n+ return;\n+ }\n+ if (cs->num_cpus >= (1 << 16)) {\n+ /* We'll hit other QEMU limits long before this one :-) */\n+ error_setg(errp, \"Number of CPUs exceeds GICv5 architectural maximum\");\n+ return;\n+ }\n+ if (cs->num_cpus != cs->num_cpu_iaffids) {\n+ error_setg(errp, \"The cpu-iaffids array property must be the same size \"\n+ \"as the cpus array property\");\n+ return;\n+ }\n+ if (cs->irsid >= (1 << 16)) {\n+ error_setg(errp, \"irsid (%u) is more than 2^16-1\", cs->irsid);\n+ return;\n+ }\n+ if (cs->spi_range > (1 << 24)) {\n+ /*\n+ * Note that IRS_IDR5.SPI_RANGE is a 25 bit field but the largest\n+ * architecturally permitted value is 2^24 (not 2^25-1), hence\n+ * use of > in the range check.\n+ */\n+ error_setg(errp, \"spi-range (%u) is more than 2^24\", cs->spi_range);\n+ return;\n+ }\n+ if (cs->spi_irs_range == GICV5_SPI_IRS_RANGE_NOT_SET) {\n+ /* spi-irs-range defaults to same as spi-range */\n+ cs->spi_irs_range = cs->spi_range;\n+ }\n+ if (cs->spi_irs_range > (1 << 24)) {\n+ /* Similarly IRS_IDR6.SPI_IRS_RANGE */\n+ error_setg(errp, \"spi-irs-range (%u) is more than 2^24\",\n+ cs->spi_irs_range);\n+ return;\n+ }\n+ if (cs->spi_base >= (1 << 24)) {\n+ /* IRS_IDR7.SPI_BASE is a 24-bit field, so range check is >= */\n+ error_setg(errp, \"spi-base (%u) is more than 2^24-1\", cs->spi_base);\n+ return;\n+ }\n+ /* range checks above mean we know this addition won't overflow */\n+ if (cs->spi_base + cs->spi_irs_range > cs->spi_range) {\n+ error_setg(errp, \"spi-base (%u) + spi-irs-range (%u) is \"\n+ \"more than spi-range (%u)\",\n+ cs->spi_base, cs->spi_irs_range, cs->spi_range);\n+ return;\n+ }\n+\n+ trace_gicv5_common_realize(cs->irsid, cs->num_cpus,\n+ cs->spi_base, cs->spi_irs_range, cs->spi_range);\n+}\n+\n+static const Property arm_gicv5_common_properties[] = {\n+ DEFINE_PROP_LINK_ARRAY(\"cpus\", GICv5Common, num_cpus,\n+ cpus, TYPE_ARM_CPU, ARMCPU *),\n+ DEFINE_PROP_ARRAY(\"cpu-iaffids\", GICv5Common, num_cpu_iaffids,\n+ cpu_iaffids, qdev_prop_uint32, uint32_t),\n+ DEFINE_PROP_UINT32(\"irsid\", GICv5Common, irsid, 0),\n+ DEFINE_PROP_UINT32(\"spi-range\", GICv5Common, spi_range, 0),\n+ DEFINE_PROP_UINT32(\"spi-base\", GICv5Common, spi_base, 0),\n+ DEFINE_PROP_UINT32(\"spi-irs-range\", GICv5Common, spi_irs_range,\n+ GICV5_SPI_IRS_RANGE_NOT_SET),\n+};\n+\n static void gicv5_common_class_init(ObjectClass *oc, const void *data)\n {\n ResettableClass *rc = RESETTABLE_CLASS(oc);\n+ DeviceClass *dc = DEVICE_CLASS(oc);\n \n rc->phases.hold = gicv5_common_reset_hold;\n+\n+ dc->realize = gicv5_common_realize;\n+ device_class_set_props(dc, arm_gicv5_common_properties);\n }\ndiff --git a/hw/intc/trace-events b/hw/intc/trace-events\nindex edd3c49c5f..54777f6da3 100644\n--- a/hw/intc/trace-events\n+++ b/hw/intc/trace-events\n@@ -233,6 +233,9 @@ gicv5_badread(const char *domain, uint64_t offset, unsigned size) \"GICv5 IRS %s\n gicv5_write(const char *domain, uint64_t offset, uint64_t data, unsigned size) \"GICv5 IRS %s config frame write: offset 0x%\" PRIx64 \" data 0x%\" PRIx64 \" size %u\"\n gicv5_badwrite(const char *domain, uint64_t offset, uint64_t data, unsigned size) \"GICv5 IRS %s config frame write: offset 0x%\" PRIx64 \" data 0x%\" PRIx64 \" size %u: error\"\n \n+# arm_gicv5_common.c\n+gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base, uint32_t spi_irs_range, uint32_t spi_range) \"GICv5 IRS realized: IRS ID %u, %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u\"\n+\n # armv7m_nvic.c\n nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) \"NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d\"\n nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) \"NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d\"\ndiff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5_common.h\nindex b7a17aac31..ea01b2a1db 100644\n--- a/include/hw/intc/arm_gicv5_common.h\n+++ b/include/hw/intc/arm_gicv5_common.h\n@@ -12,10 +12,24 @@\n #include \"qom/object.h\"\n #include \"hw/core/sysbus.h\"\n #include \"hw/intc/arm_gicv5_types.h\"\n+#include \"target/arm/cpu-qom.h\"\n \n /*\n * QEMU interface:\n *\n+ * + QOM array property \"cpus\": CPUState pointers to each CPU\n+ * connected to this IRS.\n+ * + QOM array property \"cpu-iaffids\": array of uint32_t giving the\n+ * IAFFID for each CPU in the \"cpus\" property array\n+ * + QOM property \"irsid\": unique identifier for this IRS in the system\n+ * (this is IRS_IDR0.IRSID); default is 0\n+ * + QOM property \"spi-range\": total number of SPIs in the system\n+ * IRS (this is IRS_IDR5.SPI_RANGE); must be set\n+ * + QOM property \"spi-base\": minimum SPI INTID.ID implemented on this\n+ * IRS (this is IRS_IDR7.SPI_BASE); default is 0\n+ * + QOM property \"spi-irs-range\": number of SPI INTID.ID managed on this\n+ * IRS (this is IRS_IDR6.SPI_IRS_RANGE); defaults to value of spi-range\n+ *\n * sysbus MMIO regions (in order matching IRS_IDR0.INT_DOM encoding):\n * - IRS config frame for the Secure Interrupt Domain\n * - IRS config frame for the Non-secure Interrupt Domain\n@@ -47,6 +61,17 @@ struct GICv5Common {\n \n /* Bits here are set for each physical interrupt domain implemented */\n uint8_t implemented_domains;\n+\n+ /* Properties */\n+ uint32_t num_cpus;\n+ ARMCPU **cpus;\n+ uint32_t num_cpu_iaffids;\n+ uint32_t *cpu_iaffids;\n+\n+ uint32_t irsid;\n+ uint32_t spi_base;\n+ uint32_t spi_irs_range;\n+ uint32_t spi_range;\n };\n \n struct GICv5CommonClass {\n", "prefixes": [ "v2", "07/65" ] }