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GET /api/patches/2216932/?format=api
{ "id": 2216932, "url": "http://patchwork.ozlabs.org/api/patches/2216932/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-23-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-23-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:17", "name": "[v2,22/65] target/arm: GICv5 cpuif: Implement GIC CD* insns for setting config", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "29e5b2ead3fa49d6f14bc99d08936ea82434f5bc", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-23-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216932/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216932/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=TGnF7eNs;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyyP4Sbjz1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:26:21 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65C1-0006kH-7D; Fri, 27 Mar 2026 07:17:33 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bu-0006ZZ-Fr\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:26 -0400", "from mail-wr1-x435.google.com ([2a00:1450:4864:20::435])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bs-0007we-Ed\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:26 -0400", "by mail-wr1-x435.google.com with SMTP id\n ffacd0b85a97d-43b5bded412so1432365f8f.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:23 -0700 (PDT)", "from lanath.. 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These are all simple wrappers around the\nequivalent gicv5_set_* functions, like GIC CDPRI.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/tcg/gicv5-cpuif.c | 108 +++++++++++++++++++++++++++++++++++\n 1 file changed, 108 insertions(+)", "diff": "diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 0c2bba5ce9..0c4349f8a7 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -16,6 +16,25 @@ FIELD(GIC_CDPRI, ID, 0, 24)\n FIELD(GIC_CDPRI, TYPE, 29, 3)\n FIELD(GIC_CDPRI, PRIORITY, 35, 5)\n \n+FIELD(GIC_CDDIS, ID, 0, 24)\n+FIELD(GIC_CDDIS, TYPE, 29, 3)\n+\n+FIELD(GIC_CDEN, ID, 0, 24)\n+FIELD(GIC_CDEN, TYPE, 29, 3)\n+\n+FIELD(GIC_CDAFF, ID, 0, 24)\n+FIELD(GIC_CDAFF, IRM, 28, 1)\n+FIELD(GIC_CDAFF, TYPE, 29, 3)\n+FIELD(GIC_CDAFF, IAFFID, 32, 16)\n+\n+FIELD(GIC_CDPEND, ID, 0, 24)\n+FIELD(GIC_CDPEND, TYPE, 29, 3)\n+FIELD(GIC_CDPEND, PENDING, 32, 1)\n+\n+FIELD(GIC_CDHM, ID, 0, 24)\n+FIELD(GIC_CDHM, TYPE, 29, 3)\n+FIELD(GIC_CDHM, HM, 32, 1)\n+\n static GICv5Common *gicv5_get_gic(CPUARMState *env)\n {\n return env->gicv5state;\n@@ -51,6 +70,30 @@ static GICv5Domain gicv5_current_phys_domain(CPUARMState *env)\n return gicv5_logical_domain(env);\n }\n \n+static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ GICv5Common *gic = gicv5_get_gic(env);\n+ GICv5IntType type = FIELD_EX64(value, GIC_CDDIS, TYPE);\n+ uint32_t id = FIELD_EX64(value, GIC_CDDIS, ID);\n+ bool virtual = false;\n+ GICv5Domain domain = gicv5_current_phys_domain(env);\n+\n+ gicv5_set_enabled(gic, id, false, domain, type, virtual);\n+}\n+\n+static void gic_cden_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ GICv5Common *gic = gicv5_get_gic(env);\n+ GICv5IntType type = FIELD_EX64(value, GIC_CDEN, TYPE);\n+ uint32_t id = FIELD_EX64(value, GIC_CDEN, ID);\n+ bool virtual = false;\n+ GICv5Domain domain = gicv5_current_phys_domain(env);\n+\n+ gicv5_set_enabled(gic, id, true, domain, type, virtual);\n+}\n+\n static void gic_cdpri_write(CPUARMState *env, const ARMCPRegInfo *ri,\n uint64_t value)\n {\n@@ -64,6 +107,46 @@ static void gic_cdpri_write(CPUARMState *env, const ARMCPRegInfo *ri,\n gicv5_set_priority(gic, id, priority, domain, type, virtual);\n }\n \n+static void gic_cdaff_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ GICv5Common *gic = gicv5_get_gic(env);\n+ uint32_t iaffid = FIELD_EX64(value, GIC_CDAFF, IAFFID);\n+ GICv5RoutingMode irm = FIELD_EX64(value, GIC_CDAFF, IRM);\n+ GICv5IntType type = FIELD_EX64(value, GIC_CDAFF, TYPE);\n+ uint32_t id = FIELD_EX64(value, GIC_CDAFF, ID);\n+ bool virtual = false;\n+ GICv5Domain domain = gicv5_current_phys_domain(env);\n+\n+ gicv5_set_target(gic, id, iaffid, irm, domain, type, virtual);\n+}\n+\n+static void gic_cdpend_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ GICv5Common *gic = gicv5_get_gic(env);\n+ bool pending = FIELD_EX64(value, GIC_CDPEND, PENDING);\n+ GICv5IntType type = FIELD_EX64(value, GIC_CDPEND, TYPE);\n+ uint32_t id = FIELD_EX64(value, GIC_CDPEND, ID);\n+ bool virtual = false;\n+ GICv5Domain domain = gicv5_current_phys_domain(env);\n+\n+ gicv5_set_pending(gic, id, pending, domain, type, virtual);\n+}\n+\n+static void gic_cdhm_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ GICv5Common *gic = gicv5_get_gic(env);\n+ GICv5HandlingMode hm = FIELD_EX64(value, GIC_CDHM, HM);\n+ GICv5IntType type = FIELD_EX64(value, GIC_CDAFF, TYPE);\n+ uint32_t id = FIELD_EX64(value, GIC_CDAFF, ID);\n+ bool virtual = false;\n+ GICv5Domain domain = gicv5_current_phys_domain(env);\n+\n+ gicv5_set_handling(gic, id, hm, domain, type, virtual);\n+}\n+\n static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n /*\n * Barrier: wait until the effects of a cpuif system register\n@@ -86,11 +169,36 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,\n .access = PL1_W, .type = ARM_CP_NOP,\n },\n+ { .name = \"GIC_CDDIS\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,\n+ .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .writefn = gic_cddis_write,\n+ },\n+ { .name = \"GIC_CDEN\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,\n+ .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .writefn = gic_cden_write,\n+ },\n { .name = \"GIC_CDPRI\", .state = ARM_CP_STATE_AA64,\n .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 2,\n .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n .writefn = gic_cdpri_write,\n },\n+ { .name = \"GIC_CDAFF\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 3,\n+ .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .writefn = gic_cdaff_write,\n+ },\n+ { .name = \"GIC_CDPEND\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 4,\n+ .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .writefn = gic_cdpend_write,\n+ },\n+ { .name = \"GIC_CDHM\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 2, .opc2 = 1,\n+ .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .writefn = gic_cdhm_write,\n+ },\n };\n \n void define_gicv5_cpuif_regs(ARMCPU *cpu)\n", "prefixes": [ "v2", "22/65" ] }