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GET /api/patches/2216936/?format=api
{ "id": 2216936, "url": "http://patchwork.ozlabs.org/api/patches/2216936/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-15-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-15-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:09", "name": "[v2,14/65] target/arm: GICv5 cpuif: Initial skeleton and GSB barrier insns", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1ae1ca4f80eb0280882cc5867bd75c487ecd35e7", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-15-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216936/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216936/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=NkcC/4Il;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyzV25j9z1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:27:18 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Bs-0006XM-5p; Fri, 27 Mar 2026 07:17:24 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bo-0006SS-Bi\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:20 -0400", "from mail-wr1-x436.google.com ([2a00:1450:4864:20::436])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bl-0007sK-Bj\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:19 -0400", "by mail-wr1-x436.google.com with SMTP id\n ffacd0b85a97d-439bc14dcf4so2271077f8f.1\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:16 -0700 (PDT)", "from lanath.. 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helo=mail-wr1-x436.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "In the GICv5 architecture, part of the GIC is implemented inside the\nCPU: this is the CPU interface, which presents software with system\ninstructions and system registers, and communicates with the external\npart of the GIC (the Interrupt Routing Service, IRS) via an\narchitected stream interface where both sides can send commands and\nreceive responses.\n\nAdd the initial source files for the GICv5 CPU interface, with\ninitial content implementing just the two GSB GIC barrier\ninstructions, which are no-ops for QEMU.\n\nSince we will not initially implement virtualization or the \"legacy\nGICv3\" interface that can be provided to a VM guest, we don't have\nthe ICH_VCTLR_EL2 register and do not need to implement an accessfn\nfor the \"trap if at EL1 and EL2 enabled and legacy GICv3 is enabled\"\nhandling. We will come back and add this later as part of the\nlegacy-GICv3 code.\n\n(The GICv3 has a similar architecture with part of the GIC being in\nthe CPU and part external; for QEMU we implemented the CPU interface\nin hw/intc/, but in retrospect I think this was something of a design\nmistake, and for GICv5 I am going to stick a bit closer to how the\nhardware architecture splits things up; hence this code is in\ntarget/arm.)\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/cpu-features.h | 6 +++++\n target/arm/helper.c | 1 +\n target/arm/internals.h | 3 +++\n target/arm/tcg/gicv5-cpuif.c | 43 ++++++++++++++++++++++++++++++++++++\n target/arm/tcg/meson.build | 1 +\n 5 files changed, 54 insertions(+)\n create mode 100644 target/arm/tcg/gicv5-cpuif.c", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex b683c9551a..e391b394ba 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -280,6 +280,7 @@ FIELD(ID_AA64PFR1, PFAR, 60, 4)\n FIELD(ID_AA64PFR2, MTEPERM, 0, 4)\n FIELD(ID_AA64PFR2, MTESTOREONLY, 4, 4)\n FIELD(ID_AA64PFR2, MTEFAR, 8, 4)\n+FIELD(ID_AA64PFR2, GCIE, 12, 4)\n FIELD(ID_AA64PFR2, FPMR, 32, 4)\n \n FIELD(ID_AA64MMFR0, PARANGE, 0, 4)\n@@ -1159,6 +1160,11 @@ static inline bool isar_feature_aa64_gcs(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64PFR1, GCS) != 0;\n }\n \n+static inline bool isar_feature_aa64_gcie(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64PFR2, GCIE) != 0;\n+}\n+\n static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)\n {\n return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >= 1;\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 7389f2988c..8faca360fc 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6310,6 +6310,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)\n if (tcg_enabled()) {\n define_tlb_insn_regs(cpu);\n define_at_insn_regs(cpu);\n+ define_gicv5_cpuif_regs(cpu);\n }\n #endif\n \ndiff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 8ec2750847..9bde58cf00 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -1797,6 +1797,9 @@ void define_pm_cpregs(ARMCPU *cpu);\n /* Add the cpreg definitions for GCS cpregs */\n void define_gcs_cpregs(ARMCPU *cpu);\n \n+/* Add the cpreg definitions for the GICv5 CPU interface */\n+void define_gicv5_cpuif_regs(ARMCPU *cpu);\n+\n /* Effective value of MDCR_EL2 */\n static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)\n {\ndiff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nnew file mode 100644\nindex 0000000000..7392a98c49\n--- /dev/null\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -0,0 +1,43 @@\n+/*\n+ * GICv5 CPU interface\n+ *\n+ * Copyright (c) 2025 Linaro Limited\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"cpu.h\"\n+#include \"internals.h\"\n+#include \"cpregs.h\"\n+\n+static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n+ /*\n+ * Barrier: wait until the effects of a cpuif system register\n+ * write have definitely made it to the IRS (and will thus show up\n+ * in cpuif reads from the IRS by this or other CPUs and in the\n+ * status of IRQ, FIQ etc). For QEMU we do all interaction with\n+ * the IRS synchronously, so we can make this a nop.\n+ */\n+ { .name = \"GSB_SYS\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 0,\n+ .access = PL1_W, .type = ARM_CP_NOP,\n+ },\n+ /*\n+ * Barrier: wait until the effects of acknowledging an interrupt\n+ * (via GICR CDIA or GICR CDNMIA) are visible, including the\n+ * effect on the {IRQ,FIQ,vIRQ,vFIQ} pending state. This is a\n+ * weaker version of GSB SYS. Again, for QEMU this is a nop.\n+ */\n+ { .name = \"GSB_ACK\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,\n+ .access = PL1_W, .type = ARM_CP_NOP,\n+ },\n+};\n+\n+void define_gicv5_cpuif_regs(ARMCPU *cpu)\n+{\n+ if (cpu_isar_feature(aa64_gcie, cpu)) {\n+ define_arm_cp_regs(cpu, gicv5_cpuif_reginfo);\n+ }\n+}\ndiff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build\nindex 5f59156055..a67911f8dc 100644\n--- a/target/arm/tcg/meson.build\n+++ b/target/arm/tcg/meson.build\n@@ -62,6 +62,7 @@ arm_common_ss.add(files(\n arm_common_system_ss.add(files(\n 'cpregs-at.c',\n 'debug.c',\n+ 'gicv5-cpuif.c',\n 'hflags.c',\n 'neon_helper.c',\n 'psci.c',\n", "prefixes": [ "v2", "14/65" ] }