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GET /api/patches/2216900/?format=api
{ "id": 2216900, "url": "http://patchwork.ozlabs.org/api/patches/2216900/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-26-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-26-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:20", "name": "[v2,25/65] hw/intc/arm_gicv5: Implement gicv5_request_config()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "dac059075662fc18e1d865d6b41c7d3801aae43b", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-26-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216900/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216900/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=BqguwpEn;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhysw6jrvz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:22:28 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65C3-0006nR-AK; Fri, 27 Mar 2026 07:17:35 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bx-0006gX-NJ\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:30 -0400", "from mail-wm1-x331.google.com ([2a00:1450:4864:20::331])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bv-0007yC-Fn\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:29 -0400", "by mail-wm1-x331.google.com with SMTP id\n 5b1f17b1804b1-48558d6ef83so18687375e9.3\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:27 -0700 (PDT)", "from lanath.. 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27 Mar 2026 11:16:20 +0000", "Message-ID": "<20260327111700.795099-26-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327111700.795099-1-peter.maydell@linaro.org>", "References": "<20260327111700.795099-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::331;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Implement the gicv5_request_config() function, which corresponds to\nthe RequestConfig command and its RequestConfigAck reply.\n\nWe provide read_l2_iste() as a separate function to keep the \"access\nthe in-guest-memory data structure\" layer separate from the \"operate\non the L2_ISTE values\" layer.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/intc/arm_gicv5.c | 102 +++++++++++++++++++++++++++++\n hw/intc/trace-events | 1 +\n include/hw/intc/arm_gicv5_stream.h | 24 +++++++\n 3 files changed, 127 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex 9ca1826253..04d4391ae5 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -297,6 +297,19 @@ FIELD(L2_ISTE, HWU, 9, 2)\n FIELD(L2_ISTE, PRIORITY, 11, 5)\n FIELD(L2_ISTE, IAFFID, 16, 16)\n \n+/*\n+ * Format used for gicv5_request_config() return value, which matches\n+ * the ICC_ICSR_EL1 bit layout.\n+ */\n+FIELD(ICSR, F, 0, 1)\n+FIELD(ICSR, ENABLED, 1, 1)\n+FIELD(ICSR, PENDING, 2, 1)\n+FIELD(ICSR, IRM, 3, 1)\n+FIELD(ICSR, ACTIVE, 4, 1)\n+FIELD(ICSR, HM, 5, 1)\n+FIELD(ICSR, PRIORITY, 11, 5)\n+FIELD(ICSR, IAFFID, 32, 16)\n+\n static MemTxAttrs irs_txattrs(GICv5Common *cs, GICv5Domain domain)\n {\n /*\n@@ -713,6 +726,95 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, uint32_t iaffid,\n }\n }\n \n+static uint64_t l2_iste_to_icsr(GICv5Common *cs, const GICv5ISTConfig *cfg,\n+ uint32_t id)\n+{\n+ uint64_t icsr = 0;\n+ const uint32_t *l2_iste_p;\n+ L2_ISTE_Handle h;\n+\n+ l2_iste_p = get_l2_iste(cs, cfg, id, &h);\n+ if (!l2_iste_p) {\n+ return R_ICSR_F_MASK;\n+ }\n+\n+ /*\n+ * The field locations in the L2 ISTE do not line up with the\n+ * corresponding fields in the ICC_ICSR_EL1 register, so we need\n+ * to extract and deposit them individually.\n+ */\n+ icsr = FIELD_DP64(icsr, ICSR, F, 0);\n+ icsr = FIELD_DP64(icsr, ICSR, ENABLED, FIELD_EX32(*l2_iste_p, L2_ISTE, ENABLE));\n+ icsr = FIELD_DP64(icsr, ICSR, PENDING, FIELD_EX32(*l2_iste_p, L2_ISTE, PENDING));\n+ icsr = FIELD_DP64(icsr, ICSR, IRM, FIELD_EX32(*l2_iste_p, L2_ISTE, IRM));\n+ icsr = FIELD_DP64(icsr, ICSR, ACTIVE, FIELD_EX32(*l2_iste_p, L2_ISTE, ACTIVE));\n+ icsr = FIELD_DP64(icsr, ICSR, HM, FIELD_EX32(*l2_iste_p, L2_ISTE, HM));\n+ icsr = FIELD_DP64(icsr, ICSR, PRIORITY, FIELD_EX32(*l2_iste_p, L2_ISTE, PRIORITY));\n+ icsr = FIELD_DP64(icsr, ICSR, IAFFID, FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID));\n+\n+ return icsr;\n+}\n+\n+static uint64_t spi_state_to_icsr(GICv5SPIState *spi)\n+{\n+ uint64_t icsr = 0;\n+\n+ icsr = FIELD_DP64(icsr, ICSR, F, 0);\n+ icsr = FIELD_DP64(icsr, ICSR, ENABLED, spi->enabled);\n+ icsr = FIELD_DP64(icsr, ICSR, PENDING, spi->pending);\n+ icsr = FIELD_DP64(icsr, ICSR, IRM, spi->irm);\n+ icsr = FIELD_DP64(icsr, ICSR, ACTIVE, spi->active);\n+ icsr = FIELD_DP64(icsr, ICSR, HM, spi->hm);\n+ icsr = FIELD_DP64(icsr, ICSR, PRIORITY, spi->priority);\n+ icsr = FIELD_DP64(icsr, ICSR, IAFFID, spi->iaffid);\n+\n+ return icsr;\n+}\n+\n+uint64_t gicv5_request_config(GICv5Common *cs, uint32_t id, GICv5Domain domain,\n+ GICv5IntType type, bool virtual)\n+{\n+ GICv5 *s = ARM_GICV5(cs);\n+ uint64_t icsr;\n+\n+ if (virtual) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_request_config: tried to \"\n+ \"read config of a virtual interrupt\\n\");\n+ return R_ICSR_F_MASK;\n+ }\n+\n+ switch (type) {\n+ case GICV5_LPI:\n+ {\n+ const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain];\n+\n+ icsr = l2_iste_to_icsr(cs, cfg, id);\n+ trace_gicv5_request_config(domain_name[domain], inttype_name(type),\n+ virtual, id, icsr);\n+ return icsr;\n+ }\n+ case GICV5_SPI:\n+ {\n+ GICv5SPIState *spi = gicv5_spi_state(cs, id, domain);\n+\n+ if (!spi) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_request_config: tried to \"\n+ \"read config of unreachable SPI %d\\n\", id);\n+ return R_ICSR_F_MASK;\n+ }\n+\n+ icsr = spi_state_to_icsr(spi);\n+ trace_gicv5_request_config(domain_name[domain], inttype_name(type),\n+ virtual, id, icsr);\n+ return icsr;\n+ }\n+ default:\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_request_config: tried to \"\n+ \"read config of bad interrupt type %d\\n\", type);\n+ return R_ICSR_F_MASK;\n+ }\n+}\n+\n static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t value)\n {\n GICv5Common *cs = ARM_GICV5_COMMON(s);\ndiff --git a/hw/intc/trace-events b/hw/intc/trace-events\nindex 37ca6e8e12..409935e15a 100644\n--- a/hw/intc/trace-events\n+++ b/hw/intc/trace-events\n@@ -240,6 +240,7 @@ gicv5_set_enabled(const char *domain, const char *type, bool virtual, uint32_t i\n gicv5_set_pending(const char *domain, const char *type, bool virtual, uint32_t id, bool pending) \"GICv5 IRS SetPending %s %s virtual:%d ID %u pending %d\"\n gicv5_set_handling(const char *domain, const char *type, bool virtual, uint32_t id, int handling) \"GICv5 IRS SetHandling %s %s virtual:%d ID %u handling %d\"\n gicv5_set_target(const char *domain, const char *type, bool virtual, uint32_t id, uint32_t iaffid, int irm) \"GICv5 IRS SetTarget %s %s virtual:%d ID %u IAFFID %u routingmode %d\"\n+gicv5_request_config(const char *domain, const char *type, bool virtual, uint32_t id, uint64_t icsr) \"GICv5 IRS RequestConfig %s %s virtual:%d ID %u ICSR 0x%\" PRIx64\n \n # arm_gicv5_common.c\n gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base, uint32_t spi_irs_range, uint32_t spi_range) \"GICv5 IRS realized: IRS ID %u, %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u\"\ndiff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5_stream.h\nindex af2e1851c2..670423fdad 100644\n--- a/include/hw/intc/arm_gicv5_stream.h\n+++ b/include/hw/intc/arm_gicv5_stream.h\n@@ -126,4 +126,28 @@ void gicv5_set_handling(GICv5Common *cs, uint32_t id,\n void gicv5_set_target(GICv5Common *cs, uint32_t id, uint32_t iaffid,\n GICv5RoutingMode irm, GICv5Domain domain,\n GICv5IntType type, bool virtual);\n+\n+/**\n+ * gicv5_request_config\n+ * @cs: GIC IRS to send command to\n+ * @id: interrupt ID\n+ * @domain: interrupt domain to act on\n+ * @type: interrupt type (LPI or SPI)\n+ * @virtual: true if this is a virtual interrupt\n+ *\n+ * Query the current configuration of an interrupt; matches stream\n+ * interface RequestConfig command from CPUIF to IRS and the\n+ * RequestConfigAck reply to it.\n+ *\n+ * In the real stream protocol, the RequestConfigAck packet has the\n+ * same information as the register but in a different order; we use\n+ * the register order, not the packet order, so we don't need to\n+ * unpack and repack in the cpuif.\n+ *\n+ * Returns: the config of the interrupt, in the format used by\n+ * ICC_ICSR_EL1.\n+ */\n+uint64_t gicv5_request_config(GICv5Common *cs, uint32_t id, GICv5Domain domain,\n+ GICv5IntType type, bool virtual);\n+\n #endif\n", "prefixes": [ "v2", "25/65" ] }