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GET /api/patches/2216937/?format=api
{ "id": 2216937, "url": "http://patchwork.ozlabs.org/api/patches/2216937/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-18-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-18-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:12", "name": "[v2,17/65] hw/intc/arm_gicv5: Cache LPI IST config in a struct", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2ba82a71ab76241e5be056f7ef342d3033ec9454", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-18-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216937/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216937/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ZqI88ilJ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyzW3NcYz1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:27:19 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Bt-0006Yp-TG; Fri, 27 Mar 2026 07:17:25 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bq-0006Ux-EC\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:22 -0400", "from mail-wr1-x434.google.com ([2a00:1450:4864:20::434])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bo-0007uC-3C\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:22 -0400", "by mail-wr1-x434.google.com with SMTP id\n ffacd0b85a97d-43b98652f05so862135f8f.1\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:19 -0700 (PDT)", "from lanath.. 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We would like to be able to write\ngeneric code that can manipulate any of these ISTs. Define a struct\nwhich captures the config information for an IST, and cache the\nIRS_IST_CFGR/IRS_IST_BASER data into this format when the guest sets\nthe VALID bit.\n\nThis also allows us to enforce the correct handling of reserved and\nout-of-range values, and expand the encodings of sizes into a more\nconvenient format for later use.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5.c | 64 +++++++++++++++++++++++++++++++++++++\n hw/intc/trace-events | 2 ++\n include/hw/intc/arm_gicv5.h | 12 +++++++\n 3 files changed, 78 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex cbb35c0270..172c5be0d4 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -278,9 +278,68 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t value)\n }\n cs->irs_ist_baser[domain] = FIELD_DP64(cs->irs_ist_baser[domain],\n IRS_IST_BASER, VALID, valid);\n+ s->phys_lpi_config[domain].valid = false;\n+ trace_gicv5_ist_invalid(domain_name[domain]);\n return;\n }\n cs->irs_ist_baser[domain] = value;\n+\n+ if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) {\n+ /*\n+ * If the guest just set VALID then capture data into config struct,\n+ * sanitize the reserved values, and expand fields out into byte counts.\n+ */\n+ GICv5ISTConfig *cfg = &s->phys_lpi_config[domain];\n+ uint8_t istbits, l2bits, l2_idx_bits;\n+ uint8_t id_bits = FIELD_EX64(cs->irs_ist_cfgr[domain],\n+ IRS_IST_CFGR, LPI_ID_BITS);\n+ id_bits = MIN(MAX(id_bits, QEMU_GICV5_MIN_LPI_ID_BITS), QEMU_GICV5_ID_BITS);\n+\n+ switch (FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, ISTSZ)) {\n+ case 0:\n+ case 3: /* reserved: acts like the minimum required size */\n+ istbits = 2;\n+ break;\n+ case 1:\n+ istbits = 3;\n+ break;\n+ case 2:\n+ istbits = 4;\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+ switch (FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, L2SZ)) {\n+ case 0:\n+ case 3: /* reserved; CONSTRAINED UNPREDICTABLE */\n+ l2bits = 12; /* 4K: 12 bits */\n+ break;\n+ case 1:\n+ l2bits = 14; /* 16K: 14 bits */\n+ break;\n+ case 2:\n+ l2bits = 16; /* 64K: 16 bits */\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+ /*\n+ * Calculate how many bits of an ID index the L2 table\n+ * (e.g. if we need 14 bits to index each byte in a 16K L2 table,\n+ * but each entry is 4 bytes wide then we need 14 - 2 = 12 bits\n+ * to index an entry in the table).\n+ */\n+ l2_idx_bits = l2bits - istbits;\n+ cfg->base = cs->irs_ist_baser[domain] & R_IRS_IST_BASER_ADDR_MASK;\n+ cfg->id_bits = id_bits;\n+ cfg->istsz = 1 << istbits;\n+ cfg->l2_idx_bits = l2_idx_bits;\n+ cfg->structure = FIELD_EX64(cs->irs_ist_cfgr[domain],\n+ IRS_IST_CFGR, STRUCTURE);\n+ cfg->valid = true;\n+ trace_gicv5_ist_valid(domain_name[domain], cfg->base, cfg->id_bits,\n+ cfg->l2_idx_bits, cfg->istsz, cfg->structure);\n+ }\n }\n \n static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,\n@@ -553,6 +612,11 @@ static void gicv5_reset_hold(Object *obj, ResetType type)\n if (c->parent_phases.hold) {\n c->parent_phases.hold(obj, type);\n }\n+\n+ /* IRS_IST_BASER and IRS_IST_CFGR reset to 0, clear cached info */\n+ for (int i = 0; i < NUM_GICV5_DOMAINS; i++) {\n+ s->phys_lpi_config[i].valid = false;\n+ }\n }\n \n static void gicv5_set_idregs(GICv5Common *cs)\ndiff --git a/hw/intc/trace-events b/hw/intc/trace-events\nindex 0797a23c1a..80fc47794b 100644\n--- a/hw/intc/trace-events\n+++ b/hw/intc/trace-events\n@@ -233,6 +233,8 @@ gicv5_badread(const char *domain, uint64_t offset, unsigned size) \"GICv5 IRS %s\n gicv5_write(const char *domain, uint64_t offset, uint64_t data, unsigned size) \"GICv5 IRS %s config frame write: offset 0x%\" PRIx64 \" data 0x%\" PRIx64 \" size %u\"\n gicv5_badwrite(const char *domain, uint64_t offset, uint64_t data, unsigned size) \"GICv5 IRS %s config frame write: offset 0x%\" PRIx64 \" data 0x%\" PRIx64 \" size %u: error\"\n gicv5_spi(uint32_t id, int level) \"GICv5 SPI ID %u asserted at level %d\"\n+gicv5_ist_valid(const char *domain, uint64_t base, uint8_t id_bits, uint8_t l2_idx_bits, uint8_t istsz, bool structure) \"GICv5 IRS %s IST now valid: base 0x%\" PRIx64 \" id_bits %u l2_idx_bits %u IST entry size %u 2-level %d\"\n+gicv5_ist_invalid(const char *domain) \"GICv5 IRS %s IST no longer valid\"\n \n # arm_gicv5_common.c\n gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base, uint32_t spi_irs_range, uint32_t spi_range) \"GICv5 IRS realized: IRS ID %u, %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u\"\ndiff --git a/include/hw/intc/arm_gicv5.h b/include/hw/intc/arm_gicv5.h\nindex 42ccef8474..f6ecd9c323 100644\n--- a/include/hw/intc/arm_gicv5.h\n+++ b/include/hw/intc/arm_gicv5.h\n@@ -17,11 +17,23 @@\n \n OBJECT_DECLARE_TYPE(GICv5, GICv5Class, ARM_GICV5)\n \n+typedef struct GICv5ISTConfig {\n+ hwaddr base; /* Base address */\n+ uint8_t id_bits; /* number of bits in an ID for this table */\n+ uint8_t l2_idx_bits; /* number of ID bits that index into L2 table */\n+ uint8_t istsz; /* L2 ISTE size in bytes */\n+ bool structure; /* true if using 2-level table */\n+ bool valid; /* true if this table is valid and usable */\n+} GICv5ISTConfig;\n+\n /*\n * This class is for TCG-specific state for the GICv5.\n */\n struct GICv5 {\n GICv5Common parent_obj;\n+\n+ /* This is the info from IRS_IST_BASER and IRS_IST_CFGR */\n+ GICv5ISTConfig phys_lpi_config[NUM_GICV5_DOMAINS];\n };\n \n struct GICv5Class {\n", "prefixes": [ "v2", "17/65" ] }