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GET /api/patches/2216869/?format=api
{ "id": 2216869, "url": "http://patchwork.ozlabs.org/api/patches/2216869/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-31-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-31-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:25", "name": "[v2,30/65] hw/intc/arm_gicv5: Implement IRS_SYNCR and IRS_SYNC_STATUSR", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "af38ac904e3822bdd12c262e80ad36876f39f726", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-31-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216869/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216869/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=gZws7ldr;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhymf1fGnz1y1x\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:17:54 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65C5-0006pc-0M; Fri, 27 Mar 2026 07:17:37 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C2-0006m4-4h\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:34 -0400", "from mail-wm1-x335.google.com ([2a00:1450:4864:20::335])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C0-00081i-62\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:33 -0400", "by mail-wm1-x335.google.com with SMTP id\n 5b1f17b1804b1-486fb14227cso24721295e9.3\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:31 -0700 (PDT)", "from lanath.. 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This means that in-flight interrupt events are\nguaranteed to have been delivered.\n\nSince QEMU's implementation is entirely synchronous, syncs are a\nno-op for us. This means we can ignore writes to IRS_SYNCR and\nalways report \"sync complete\" via the IDLE bit in IRS_SYNC_STATUSR.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5.c | 7 +++++++\n 1 file changed, 7 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex 3f397d9115..7b0d9e16c4 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -1087,6 +1087,10 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,\n case A_IRS_CR1:\n *data = cs->irs_cr1[domain];\n return true;\n+ case A_IRS_SYNC_STATUSR:\n+ /* Sync is a no-op for QEMU: we are always IDLE */\n+ *data = R_IRS_SYNC_STATUSR_IDLE_MASK;\n+ return true;\n }\n \n return false;\n@@ -1172,6 +1176,9 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset,\n case A_IRS_CR1:\n cs->irs_cr1[domain] = data;\n return true;\n+ case A_IRS_SYNCR:\n+ /* Sync is a no-op for QEMU: ignore write */\n+ return true;\n }\n \n return false;\n", "prefixes": [ "v2", "30/65" ] }