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GET /api/patches/2216901/?format=api
{ "id": 2216901, "url": "http://patchwork.ozlabs.org/api/patches/2216901/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-12-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-12-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:06", "name": "[v2,11/65] hw/intc/arm_gicv5: Add link property for MemoryRegion for DMA", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "abed994681b01864ae72ed1e969ab309340ab267", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-12-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216901/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216901/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=mz0jMaK6;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhysx13NVz1yFr\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:22:29 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Bp-0006Te-9o; Fri, 27 Mar 2026 07:17:21 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bk-0006Q6-Ml\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:17 -0400", "from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bi-0007qB-Eh\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:15 -0400", "by mail-wm1-x32e.google.com with SMTP id\n 5b1f17b1804b1-48700b1ba53so18914975e9.1\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:13 -0700 (PDT)", "from lanath.. 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(Notably, it\nstores per-interrupt configuration information like the interrupt\npriority and its active and pending state in an in-memory data\nstructure.) Add a link property so that the board or SoC can wire up\na MemoryRegion that we will do DMA to. We name this property\n\"sysmem\" to match the GICv3's equivalent property.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5_common.c | 8 ++++++++\n include/hw/intc/arm_gicv5_common.h | 4 ++++\n 2 files changed, 12 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c\nindex b58913b970..29cc96917e 100644\n--- a/hw/intc/arm_gicv5_common.c\n+++ b/hw/intc/arm_gicv5_common.c\n@@ -122,6 +122,12 @@ static void gicv5_common_realize(DeviceState *dev, Error **errp)\n cs->spi_base, cs->spi_irs_range, cs->spi_range);\n return;\n }\n+ if (!cs->dma) {\n+ error_setg(errp, \"sysmem link property not set\");\n+ return;\n+ }\n+\n+ address_space_init(&cs->dma_as, cs->dma, \"gicv5-sysmem\");\n \n trace_gicv5_common_realize(cs->irsid, cs->num_cpus,\n cs->spi_base, cs->spi_irs_range, cs->spi_range);\n@@ -137,6 +143,8 @@ static const Property arm_gicv5_common_properties[] = {\n DEFINE_PROP_UINT32(\"spi-base\", GICv5Common, spi_base, 0),\n DEFINE_PROP_UINT32(\"spi-irs-range\", GICv5Common, spi_irs_range,\n GICV5_SPI_IRS_RANGE_NOT_SET),\n+ DEFINE_PROP_LINK(\"sysmem\", GICv5Common, dma, TYPE_MEMORY_REGION,\n+ MemoryRegion *),\n };\n \n static void gicv5_common_class_init(ObjectClass *oc, const void *data)\ndiff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5_common.h\nindex 906870e49f..900af53b0f 100644\n--- a/include/hw/intc/arm_gicv5_common.h\n+++ b/include/hw/intc/arm_gicv5_common.h\n@@ -83,6 +83,10 @@ struct GICv5Common {\n uint32_t num_cpu_iaffids;\n uint32_t *cpu_iaffids;\n \n+ /* MemoryRegion and AS to DMA to/from for in-memory data structures */\n+ MemoryRegion *dma;\n+ AddressSpace dma_as;\n+\n uint32_t irsid;\n uint32_t spi_base;\n uint32_t spi_irs_range;\n", "prefixes": [ "v2", "11/65" ] }