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GET /api/patches/2216888/?format=api
{ "id": 2216888, "url": "http://patchwork.ozlabs.org/api/patches/2216888/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-64-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-64-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:58", "name": "[v2,63/65] hw/arm/virt: Use correct interrupt type for GICv5 SPIs in the DTB", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "693240557515da49cd59613a1e3224adc81a3847", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-64-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216888/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216888/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=W1BOGURd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyqh4D8Mz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:20:32 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65EB-0003Ed-Ii; Fri, 27 Mar 2026 07:19:47 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Cb-0007qY-TD\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:09 -0400", "from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CX-0000Hh-Sf\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:09 -0400", "by mail-wr1-x42f.google.com with SMTP id\n ffacd0b85a97d-439b7c2788dso1186502f8f.1\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:18:03 -0700 (PDT)", "from lanath.. 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This\nis different to the GICv2 and GICv3, so instead of hardcoding the\nGIC_FDT_IRQ_TYPE_SPI constant when we create \"interrupts\" bindings,\ncreate a new function gic_fdt_irq_type_spi() that returns the right\nvalue for the interrupt controller in use.\n\nFor SPIs, the INTID.ID and the trigger-mode fields of the\n\"interrupts\" property remain the same for GICv5 and the older GIC\nversions.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/arm/virt.c | 29 ++++++++++++++++++++---------\n 1 file changed, 20 insertions(+), 9 deletions(-)", "diff": "diff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex bc49cf244f..15d833ad8f 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -295,6 +295,16 @@ static bool ns_el2_virt_timer_present(void)\n arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);\n }\n \n+/*\n+ * The correct value to use in a DTB \"interrupts\" property for an SPI\n+ * depends on the GIC version.\n+ */\n+static int gic_fdt_irq_type_spi(const VirtMachineState *vms)\n+{\n+ return vms->gic_version == VIRT_GIC_VERSION_5 ?\n+ GICV5_SPI : GIC_FDT_IRQ_TYPE_SPI;\n+}\n+\n static void create_fdt(VirtMachineState *vms)\n {\n MachineState *ms = MACHINE(vms);\n@@ -1183,7 +1193,7 @@ static void create_uart(const VirtMachineState *vms, int uart,\n qemu_fdt_setprop_sized_cells(ms->fdt, nodename, \"reg\",\n 2, base, 2, size);\n qemu_fdt_setprop_cells(ms->fdt, nodename, \"interrupts\",\n- GIC_FDT_IRQ_TYPE_SPI, irq,\n+ gic_fdt_irq_type_spi(vms), irq,\n GIC_FDT_IRQ_FLAGS_LEVEL_HI);\n qemu_fdt_setprop_cells(ms->fdt, nodename, \"clocks\",\n vms->clock_phandle, vms->clock_phandle);\n@@ -1225,7 +1235,7 @@ static void create_rtc(const VirtMachineState *vms)\n qemu_fdt_setprop_sized_cells(ms->fdt, nodename, \"reg\",\n 2, base, 2, size);\n qemu_fdt_setprop_cells(ms->fdt, nodename, \"interrupts\",\n- GIC_FDT_IRQ_TYPE_SPI, irq,\n+ gic_fdt_irq_type_spi(vms), irq,\n GIC_FDT_IRQ_FLAGS_LEVEL_HI);\n qemu_fdt_setprop_cell(ms->fdt, nodename, \"clocks\", vms->clock_phandle);\n qemu_fdt_setprop_string(ms->fdt, nodename, \"clock-names\", \"apb_pclk\");\n@@ -1344,7 +1354,7 @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio,\n qemu_fdt_setprop_cell(ms->fdt, nodename, \"#gpio-cells\", 2);\n qemu_fdt_setprop(ms->fdt, nodename, \"gpio-controller\", NULL, 0);\n qemu_fdt_setprop_cells(ms->fdt, nodename, \"interrupts\",\n- GIC_FDT_IRQ_TYPE_SPI, irq,\n+ gic_fdt_irq_type_spi(vms), irq,\n GIC_FDT_IRQ_FLAGS_LEVEL_HI);\n qemu_fdt_setprop_cell(ms->fdt, nodename, \"clocks\", vms->clock_phandle);\n qemu_fdt_setprop_string(ms->fdt, nodename, \"clock-names\", \"apb_pclk\");\n@@ -1425,7 +1435,7 @@ static void create_virtio_devices(const VirtMachineState *vms)\n qemu_fdt_setprop_sized_cells(ms->fdt, nodename, \"reg\",\n 2, base, 2, size);\n qemu_fdt_setprop_cells(ms->fdt, nodename, \"interrupts\",\n- GIC_FDT_IRQ_TYPE_SPI, irq,\n+ gic_fdt_irq_type_spi(vms), irq,\n GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);\n qemu_fdt_setprop(ms->fdt, nodename, \"dma-coherent\", NULL, 0);\n g_free(nodename);\n@@ -1625,10 +1635,11 @@ static void create_pcie_irq_map(const MachineState *ms,\n int devfn, pin;\n uint32_t full_irq_map[4 * 4 * 10] = { 0 };\n uint32_t *irq_map = full_irq_map;\n+ const VirtMachineState *vms = VIRT_MACHINE(ms);\n \n for (devfn = 0; devfn <= 0x18; devfn += 0x8) {\n for (pin = 0; pin < 4; pin++) {\n- int irq_type = GIC_FDT_IRQ_TYPE_SPI;\n+ int irq_type = gic_fdt_irq_type_spi(vms);\n int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);\n int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;\n int i;\n@@ -1669,10 +1680,10 @@ static void create_smmuv3_dt_bindings(const VirtMachineState *vms, hwaddr base,\n qemu_fdt_setprop_sized_cells(ms->fdt, node, \"reg\", 2, base, 2, size);\n \n qemu_fdt_setprop_cells(ms->fdt, node, \"interrupts\",\n- GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,\n- GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,\n- GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,\n- GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);\n+ gic_fdt_irq_type_spi(vms), irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,\n+ gic_fdt_irq_type_spi(vms), irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,\n+ gic_fdt_irq_type_spi(vms), irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,\n+ gic_fdt_irq_type_spi(vms), irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);\n \n qemu_fdt_setprop(ms->fdt, node, \"interrupt-names\", irq_names,\n sizeof(irq_names));\n", "prefixes": [ "v2", "63/65" ] }