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GET /api/patches/2216929/?format=api
{ "id": 2216929, "url": "http://patchwork.ozlabs.org/api/patches/2216929/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-61-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-61-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:55", "name": "[v2,60/65] hw/arm/virt: Create and connect GICv5", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "683f87ef7fd7a399843d18c9589423d9195f32af", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-61-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216929/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216929/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=VNepMIzp;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyy02Tsdz1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:26:00 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Dt-0002A4-6T; Fri, 27 Mar 2026 07:19:29 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CZ-0007aO-21\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:07 -0400", "from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CV-0000EK-6V\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:06 -0400", "by mail-wm1-x32b.google.com with SMTP id\n 5b1f17b1804b1-4853c1ca73aso19230425e9.2\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:18:00 -0700 (PDT)", "from lanath.. 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We do not\nadvertise it in the ACPI tables or DTB; that will be done in a\nfollowing commit.\n\nThe user-facing gic-version property still only documents and permits\nin its setter function the existing set of possible values; we won't\npermit the user to select a GICv5 until all the code to handle it is\nin place.\n\nAlthough we currently implement only the IRS, and only for EL1,\nwe reserve space in the virt board's memory map now for all the\nregister frames that the GICv5 may use. Each interrupt domain has:\n * one IRS config register frame\n * one ITS config register frame\n * one ITS translate register frame\nand each of these frames is 64K in size and 64K aligned and must be\nat a unique address (that is, it is not permitted to have all the IRS\nconfig register frames at the same physical address in the different\nS/NS/etc physical address spaces).\n\nThe addresses and layout of these frames are entirely up to the\nimplementation: software will be passed their addresses via firmware\ndata structures (ACPI or DTB).\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/arm/virt.c | 101 ++++++++++++++++++++++++++++++++++++++++++\n include/hw/arm/virt.h | 14 ++++++\n 2 files changed, 115 insertions(+)", "diff": "diff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex 8c383d7e40..b6a04f868b 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -69,6 +69,7 @@\n #include \"hw/intc/arm_gic.h\"\n #include \"hw/intc/arm_gicv3_common.h\"\n #include \"hw/intc/arm_gicv3_its_common.h\"\n+#include \"hw/intc/arm_gicv5_common.h\"\n #include \"hw/core/irq.h\"\n #include \"kvm_arm.h\"\n #include \"whpx_arm.h\"\n@@ -184,6 +185,19 @@ static const MemMapEntry base_memmap[] = {\n [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },\n /* This redistributor space allows up to 2*64kB*123 CPUs */\n [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },\n+ /* The GICv5 uses this address range differently from GICv2/v3/v4 */\n+ [VIRT_GICV5_IRS_S] = { 0x08000000, 0x00010000 },\n+ [VIRT_GICV5_IRS_NS] = { 0x08010000, 0x00010000 },\n+ [VIRT_GICV5_IRS_EL3] = { 0x08020000, 0x00010000 },\n+ [VIRT_GICV5_IRS_REALM] = { 0x08030000, 0x00010000 },\n+ [VIRT_GICV5_ITS_S] = { 0x08040000, 0x00010000 },\n+ [VIRT_GICV5_ITS_NS] = { 0x08050000, 0x00010000 },\n+ [VIRT_GICV5_ITS_EL3] = { 0x08060000, 0x00010000 },\n+ [VIRT_GICV5_ITS_REALM] = { 0x08070000, 0x00010000 },\n+ [VIRT_GICV5_ITS_TR_S] = { 0x08080000, 0x00010000 },\n+ [VIRT_GICV5_ITS_TR_NS] = { 0x08090000, 0x00010000 },\n+ [VIRT_GICV5_ITS_TR_EL3] = { 0x080A0000, 0x00010000 },\n+ [VIRT_GICV5_ITS_TR_REALM] = { 0x080B0000, 0x00010000 },\n [VIRT_UART0] = { 0x09000000, 0x00001000 },\n [VIRT_RTC] = { 0x09010000, 0x00001000 },\n [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },\n@@ -780,6 +794,49 @@ static void create_v2m(VirtMachineState *vms)\n vms->msi_controller = VIRT_MSI_CTRL_GICV2M;\n }\n \n+static void create_gicv5(VirtMachineState *vms, MemoryRegion *mem)\n+{\n+ MachineState *ms = MACHINE(vms);\n+ SysBusDevice *gicbusdev;\n+ const char *gictype = gicv5_class_name();\n+ QList *cpulist = qlist_new(), *iaffidlist = qlist_new();\n+\n+ vms->gic = qdev_new(gictype);\n+ qdev_prop_set_uint32(vms->gic, \"spi-range\", NUM_IRQS);\n+\n+ object_property_set_link(OBJECT(vms->gic), \"sysmem\", OBJECT(mem),\n+ &error_fatal);\n+\n+ for (int i = 0; i < ms->smp.cpus; i++) {\n+ qlist_append_link(cpulist, OBJECT(qemu_get_cpu(i)));\n+ /*\n+ * GICv5 IAFFIDs must be system-wide unique across all GICs.\n+ * For virt we make them the same as the CPU index.\n+ */\n+ qlist_append_int(iaffidlist, i);\n+ }\n+ qdev_prop_set_array(vms->gic, \"cpus\", cpulist);\n+ qdev_prop_set_array(vms->gic, \"cpu-iaffids\", iaffidlist);\n+\n+ gicbusdev = SYS_BUS_DEVICE(vms->gic);\n+ sysbus_realize_and_unref(gicbusdev, &error_fatal);\n+\n+ /*\n+ * Map the IRS config frames for the interrupt domains.\n+ * At the moment we implement only the NS domain, so this is simple.\n+ */\n+ sysbus_mmio_map(gicbusdev, GICV5_ID_NS,\n+ vms->memmap[VIRT_GICV5_IRS_NS].base);\n+\n+ /*\n+ * The GICv5 does not need to wire up CPU timer IRQ outputs to the GIC\n+ * because for the GICv5 those PPIs are entirely internal to the CPU.\n+ * Nor do we need to wire up GIC IRQ/FIQ signals to the CPUs, because\n+ * that information is communicated directly between a GICv5 IRS and\n+ * the GICv5 CPU interface via our equivalent of the stream protocol.\n+ */\n+}\n+\n /*\n * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too.\n * It's permitted to have a configuration with NMI in the CPU (and thus the\n@@ -992,6 +1049,9 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)\n case VIRT_GIC_VERSION_4:\n create_gicv3(vms, mem);\n break;\n+ case VIRT_GIC_VERSION_5:\n+ create_gicv5(vms, mem);\n+ break;\n default:\n g_assert_not_reached();\n }\n@@ -1927,6 +1987,11 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)\n /*\n * Adjust MPIDR to make TCG consistent (with 64-bit KVM hosts)\n * and to improve SGI efficiency.\n+ * - GICv2 only supports 8 CPUs anyway\n+ * - GICv3 wants 16 CPUs per Aff0 because of an ICC_SGIxR\n+ * register limitation\n+ * - GICv5 has no restrictions, so we retain the GICv3 16-per-Aff0\n+ * layout because that's what KVM does\n */\n if (vms->gic_version == VIRT_GIC_VERSION_2) {\n clustersz = GIC_TARGETLIST_BITS;\n@@ -2072,6 +2137,11 @@ static VirtGICType finalize_gic_version_do(const char *accel_name,\n return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,\n gics_supported, max_cpus);\n case VIRT_GIC_VERSION_MAX:\n+ /*\n+ * We don't (currently) make 'max' select GICv5 as it is not\n+ * backwards compatible for system software with GICv3/v4 and\n+ * at time of writing not widely supported in guest kernels.\n+ */\n if (gics_supported & VIRT_GIC_VERSION_4_MASK) {\n gic_version = VIRT_GIC_VERSION_4;\n } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {\n@@ -2100,6 +2170,7 @@ static VirtGICType finalize_gic_version_do(const char *accel_name,\n case VIRT_GIC_VERSION_2:\n case VIRT_GIC_VERSION_3:\n case VIRT_GIC_VERSION_4:\n+ case VIRT_GIC_VERSION_5:\n break;\n }\n \n@@ -2124,6 +2195,12 @@ static VirtGICType finalize_gic_version_do(const char *accel_name,\n exit(1);\n }\n break;\n+ case VIRT_GIC_VERSION_5:\n+ if (!(gics_supported & VIRT_GIC_VERSION_5_MASK)) {\n+ error_report(\"%s does not support GICv5 emulation\", accel_name);\n+ exit(1);\n+ }\n+ break;\n default:\n error_report(\"logic error in finalize_gic_version\");\n exit(1);\n@@ -2175,6 +2252,10 @@ static void finalize_gic_version(VirtMachineState *vms)\n gics_supported |= VIRT_GIC_VERSION_4_MASK;\n }\n }\n+ if (!hvf_enabled() && module_object_class_by_name(\"arm-gicv5\")) {\n+ /* HVF doesn't have GICv5 support */\n+ gics_supported |= VIRT_GIC_VERSION_5_MASK;\n+ }\n } else {\n error_report(\"Unsupported accelerator, can not determine GIC support\");\n exit(1);\n@@ -2208,6 +2289,9 @@ static void finalize_msi_controller(VirtMachineState *vms)\n vms->msi_controller = VIRT_MSI_CTRL_GICV2M;\n } else if (whpx_enabled()) {\n vms->msi_controller = VIRT_MSI_CTRL_GICV2M;\n+ } else if (vms->gic_version == VIRT_GIC_VERSION_5) {\n+ /* GICv5 ITS is not yet implemented */\n+ vms->msi_controller = VIRT_MSI_CTRL_NONE;\n } else {\n vms->msi_controller = VIRT_MSI_CTRL_ITS;\n }\n@@ -2223,6 +2307,10 @@ static void finalize_msi_controller(VirtMachineState *vms)\n error_report(\"GICv2 + ITS is an invalid configuration.\");\n exit(1);\n }\n+ if (vms->gic_version == VIRT_GIC_VERSION_5) {\n+ error_report(\"GICv5 + ITS is not yet implemented.\");\n+ exit(1);\n+ }\n if (whpx_enabled()) {\n error_report(\"ITS not supported on WHPX.\");\n exit(1);\n@@ -2395,6 +2483,13 @@ static void machvirt_init(MachineState *machine)\n */\n if (vms->gic_version == VIRT_GIC_VERSION_2) {\n virt_max_cpus = GIC_NCPU;\n+ } else if (vms->gic_version == VIRT_GIC_VERSION_5) {\n+ /*\n+ * GICv5 imposes no CPU limit beyond the 16-bit IAFFID field.\n+ * The maximum number of CPUs will be limited not by this, but\n+ * by the MachineClass::max_cpus value we set earlier.\n+ */\n+ virt_max_cpus = 1 << QEMU_GICV5_IAFFID_BITS;\n } else {\n virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);\n if (vms->highmem_redists) {\n@@ -2440,6 +2535,12 @@ static void machvirt_init(MachineState *machine)\n exit(1);\n }\n \n+ if ((vms->virt || vms->secure) &&\n+ vms->gic_version == VIRT_GIC_VERSION_5) {\n+ error_report(\"mach-virt: GICv5 currently supports EL1 only\\n\");\n+ exit(1);\n+ }\n+\n create_fdt(vms);\n \n assert(possible_cpus->len == max_cpus);\ndiff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h\nindex 22bbc34ca8..0a804ddad4 100644\n--- a/include/hw/arm/virt.h\n+++ b/include/hw/arm/virt.h\n@@ -63,6 +63,18 @@ enum {\n VIRT_GIC_VCPU,\n VIRT_GIC_ITS,\n VIRT_GIC_REDIST,\n+ VIRT_GICV5_IRS_S,\n+ VIRT_GICV5_IRS_NS,\n+ VIRT_GICV5_IRS_EL3,\n+ VIRT_GICV5_IRS_REALM,\n+ VIRT_GICV5_ITS_S,\n+ VIRT_GICV5_ITS_NS,\n+ VIRT_GICV5_ITS_EL3,\n+ VIRT_GICV5_ITS_REALM,\n+ VIRT_GICV5_ITS_TR_S,\n+ VIRT_GICV5_ITS_TR_NS,\n+ VIRT_GICV5_ITS_TR_EL3,\n+ VIRT_GICV5_ITS_TR_REALM,\n VIRT_SMMU,\n VIRT_UART0,\n VIRT_MMIO,\n@@ -116,12 +128,14 @@ typedef enum VirtGICType {\n VIRT_GIC_VERSION_2 = 2,\n VIRT_GIC_VERSION_3 = 3,\n VIRT_GIC_VERSION_4 = 4,\n+ VIRT_GIC_VERSION_5 = 5,\n VIRT_GIC_VERSION_NOSEL,\n } VirtGICType;\n \n #define VIRT_GIC_VERSION_2_MASK BIT(VIRT_GIC_VERSION_2)\n #define VIRT_GIC_VERSION_3_MASK BIT(VIRT_GIC_VERSION_3)\n #define VIRT_GIC_VERSION_4_MASK BIT(VIRT_GIC_VERSION_4)\n+#define VIRT_GIC_VERSION_5_MASK BIT(VIRT_GIC_VERSION_5)\n \n struct VirtMachineClass {\n MachineClass parent;\n", "prefixes": [ "v2", "60/65" ] }