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GET /api/patches/2216904/?format=api
{ "id": 2216904, "url": "http://patchwork.ozlabs.org/api/patches/2216904/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-56-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-56-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:50", "name": "[v2,55/65] hw/intc/arm_gicv3_cpuif: Don't allow GICv3 if CPU has GICv5 cpuif", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4cc0ad825d2ef0a82fb183ec57c0fb549a35e15d", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-56-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216904/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216904/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=tQ0U+vZk;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhytG116zz1yFx\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:22:46 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65DJ-0000Cr-2O; Fri, 27 Mar 2026 07:18:53 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CT-0007RZ-P7\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:03 -0400", "from mail-wr1-x431.google.com ([2a00:1450:4864:20::431])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CO-00005M-CM\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:58 -0400", "by mail-wr1-x431.google.com with SMTP id\n ffacd0b85a97d-439bcec8613so1482460f8f.3\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:55 -0700 (PDT)", "from lanath.. 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If we find that we're trying\nto connect a GICv3 to a CPU that implements FEAT_GCIE, fail. This\nwill only happen if the board code has a bug and doesn't configure\nits CPUs and its GIC consistently.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv3.c | 2 +-\n hw/intc/arm_gicv3_cpuif.c | 14 +++++++++++++-\n hw/intc/gicv3_internal.h | 2 +-\n 3 files changed, 15 insertions(+), 3 deletions(-)", "diff": "diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c\nindex 542f81ea49..e93c1df5b4 100644\n--- a/hw/intc/arm_gicv3.c\n+++ b/hw/intc/arm_gicv3.c\n@@ -449,7 +449,7 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)\n \n gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);\n \n- gicv3_init_cpuif(s);\n+ gicv3_init_cpuif(s, errp);\n }\n \n static void arm_gicv3_class_init(ObjectClass *klass, const void *data)\ndiff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c\nindex eaf1e512ed..73e06f87d4 100644\n--- a/hw/intc/arm_gicv3_cpuif.c\n+++ b/hw/intc/arm_gicv3_cpuif.c\n@@ -16,6 +16,7 @@\n #include \"qemu/bitops.h\"\n #include \"qemu/log.h\"\n #include \"qemu/main-loop.h\"\n+#include \"qapi/error.h\"\n #include \"trace.h\"\n #include \"gicv3_internal.h\"\n #include \"hw/core/irq.h\"\n@@ -3016,7 +3017,7 @@ static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque)\n gicv3_cpuif_virt_irq_fiq_update(cs);\n }\n \n-void gicv3_init_cpuif(GICv3State *s)\n+void gicv3_init_cpuif(GICv3State *s, Error **errp)\n {\n /* Called from the GICv3 realize function; register our system\n * registers with the CPU\n@@ -3027,6 +3028,17 @@ void gicv3_init_cpuif(GICv3State *s)\n ARMCPU *cpu = ARM_CPU(qemu_get_cpu(s->first_cpu_idx + i));\n GICv3CPUState *cs = &s->cpu[i];\n \n+ if (cpu_isar_feature(aa64_gcie, cpu)) {\n+ /*\n+ * Attempt to connect GICv3 to a CPU with GICv5 cpuif\n+ * (almost certainly a bug in the board code)\n+ */\n+ error_setg(errp,\n+ \"Cannot connect GICv3 to CPU %d which has GICv5 cpuif\",\n+ i);\n+ return;\n+ }\n+\n /*\n * If the CPU doesn't define a GICv3 configuration, probably because\n * in real hardware it doesn't have one, then we use default values\ndiff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h\nindex 880dbe52d8..c01be70464 100644\n--- a/hw/intc/gicv3_internal.h\n+++ b/hw/intc/gicv3_internal.h\n@@ -722,7 +722,7 @@ void gicv3_redist_mov_vlpi(GICv3CPUState *src, uint64_t src_vptaddr,\n void gicv3_redist_vinvall(GICv3CPUState *cs, uint64_t vptaddr);\n \n void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns);\n-void gicv3_init_cpuif(GICv3State *s);\n+void gicv3_init_cpuif(GICv3State *s, Error **errp);\n \n /**\n * gicv3_cpuif_update:\n", "prefixes": [ "v2", "55/65" ] }