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GET /api/patches/2216919/?format=api
{ "id": 2216919, "url": "http://patchwork.ozlabs.org/api/patches/2216919/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-57-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-57-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:51", "name": "[v2,56/65] hw/arm/virt: Remember CPU phandles rather than looking them up by name", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "054dd4a8072cf0ccbe56062227d02ec81464d355", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-57-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216919/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216919/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=j8D3pVma;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhywc2qqBz1yFr\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:24:48 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65DS-0000NR-PZ; Fri, 27 Mar 2026 07:19:04 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CT-0007Rf-SU\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:03 -0400", "from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CO-00006q-PL\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:59 -0400", "by mail-wr1-x42d.google.com with SMTP id\n ffacd0b85a97d-439b2965d4bso1507057f8f.2\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:56 -0700 (PDT)", "from lanath.. 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::42d;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "In fdt_add_cpu_nodes(), we currently add phandles for each CPU node\nif we are going to add a topology description, and when we do, we\nre-look-up the phandle by node name when creating the topology\ndescription.\n\nFor GICv5 we will also want to refer to the CPU phandles; so always\nadd a phandle, and keep track of those phandles in the\nVirtMachineState so we don't have to look them up by name in the dtb\nevery time.\n\nThe phandle property is extra data in the final DTB, but only a tiny\namount, so it's not worth trying to carefully track the conditions\nwhen we're going to need them so we only emit them when required.\n\n(We need to change the smp_cpus variable to unsigned because\notherwise gcc thinks that we might be passing a negative number to\ng_new0() and produces an error:\n\n/usr/include/glib-2.0/glib/gmem.h:270:19: error: argument 1 range [18446744071562067968, 18446744073709551615] exceeds maximum object size 9223372036854775807 [-Werror=alloc-size-larger-than=]\n 270 | __p = g_##func##_n (__n, __s); \\\n | ^~~~~~~~~~~~~~~~~~~~~~~\n/usr/include/glib-2.0/glib/gmem.h:332:57: note: in expansion of macro ‘_G_NEW’\n 332 | #define g_new0(struct_type, n_structs) _G_NEW (struct_type, n_structs, malloc0)\n | ^~~~~~\n../../hw/arm/virt.c:469:25: note: in expansion of macro ‘g_new0’\n 469 | vms->cpu_phandles = g_new0(uint32_t, smp_cpus);\n | ^~~~~~\n\n)\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/arm/virt.c | 19 ++++++++++---------\n include/hw/arm/virt.h | 1 +\n 2 files changed, 11 insertions(+), 9 deletions(-)", "diff": "diff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex ec0d8475ca..91097e25ec 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -431,13 +431,13 @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)\n }\n }\n \n-static void fdt_add_cpu_nodes(const VirtMachineState *vms)\n+static void fdt_add_cpu_nodes(VirtMachineState *vms)\n {\n int cpu;\n int addr_cells = 1;\n const MachineState *ms = MACHINE(vms);\n const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);\n- int smp_cpus = ms->smp.cpus;\n+ unsigned int smp_cpus = ms->smp.cpus;\n \n /*\n * See Linux Documentation/devicetree/bindings/arm/cpus.yaml\n@@ -465,10 +465,13 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)\n qemu_fdt_setprop_cell(ms->fdt, \"/cpus\", \"#address-cells\", addr_cells);\n qemu_fdt_setprop_cell(ms->fdt, \"/cpus\", \"#size-cells\", 0x0);\n \n+ vms->cpu_phandles = g_new0(uint32_t, smp_cpus);\n+\n for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {\n char *nodename = g_strdup_printf(\"/cpus/cpu@%d\", cpu);\n ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));\n CPUState *cs = CPU(armcpu);\n+ uint32_t phandle;\n \n qemu_fdt_add_subnode(ms->fdt, nodename);\n qemu_fdt_setprop_string(ms->fdt, nodename, \"device_type\", \"cpu\");\n@@ -493,10 +496,9 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)\n ms->possible_cpus->cpus[cs->cpu_index].props.node_id);\n }\n \n- if (!vmc->no_cpu_topology) {\n- qemu_fdt_setprop_cell(ms->fdt, nodename, \"phandle\",\n- qemu_fdt_alloc_phandle(ms->fdt));\n- }\n+ phandle = qemu_fdt_alloc_phandle(ms->fdt);\n+ qemu_fdt_setprop_cell(ms->fdt, nodename, \"phandle\", phandle);\n+ vms->cpu_phandles[cpu] = phandle;\n \n g_free(nodename);\n }\n@@ -521,7 +523,6 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)\n qemu_fdt_add_subnode(ms->fdt, \"/cpus/cpu-map\");\n \n for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {\n- char *cpu_path = g_strdup_printf(\"/cpus/cpu@%d\", cpu);\n char *map_path;\n \n if (ms->smp.threads > 1) {\n@@ -539,10 +540,10 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)\n cpu % ms->smp.cores);\n }\n qemu_fdt_add_path(ms->fdt, map_path);\n- qemu_fdt_setprop_phandle(ms->fdt, map_path, \"cpu\", cpu_path);\n+ qemu_fdt_setprop_cell(ms->fdt, map_path, \"cpu\",\n+ vms->cpu_phandles[cpu]);\n \n g_free(map_path);\n- g_free(cpu_path);\n }\n }\n }\ndiff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h\nindex 5fcbd1c76f..22bbc34ca8 100644\n--- a/include/hw/arm/virt.h\n+++ b/include/hw/arm/virt.h\n@@ -171,6 +171,7 @@ struct VirtMachineState {\n uint32_t gic_phandle;\n uint32_t msi_phandle;\n uint32_t iommu_phandle;\n+ uint32_t *cpu_phandles;\n int psci_conduit;\n uint8_t virtio_transports;\n hwaddr highest_gpa;\n", "prefixes": [ "v2", "56/65" ] }