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GET /api/patches/2216910/?format=api
{ "id": 2216910, "url": "http://patchwork.ozlabs.org/api/patches/2216910/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-41-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-41-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:35", "name": "[v2,40/65] target/arm: GICv5 cpuif: Implement PPI priority registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1ff88caf442f6b8c5eeba41ae364be67658c51eb", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-41-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216910/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216910/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=K0GALIVU;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyv93x6fz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:23:33 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65CD-00071s-8W; Fri, 27 Mar 2026 07:17:45 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CC-00070f-21\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:44 -0400", "from mail-wm1-x333.google.com ([2a00:1450:4864:20::333])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CA-0008FE-07\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:43 -0400", "by mail-wm1-x333.google.com with SMTP id\n 5b1f17b1804b1-48557c8ad47so14776045e9.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:41 -0700 (PDT)", "from lanath.. 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This would be a lot of duplication if we\nwrote it out statically in the array, so instead create each register\nvia a loop in define_gicv5_cpuif_regs().\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/cpu.h | 2 ++\n target/arm/tcg/gicv5-cpuif.c | 23 +++++++++++++++++++++++\n 2 files changed, 25 insertions(+)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 915a225f8e..b97f659352 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -608,6 +608,8 @@ typedef struct CPUArchState {\n uint64_t ppi_hm[GICV5_NUM_PPIS / 64];\n uint64_t ppi_pend[GICV5_NUM_PPIS / 64];\n uint64_t ppi_enable[GICV5_NUM_PPIS / 64];\n+ /* The PRIO regs have 1 byte per PPI, so 8 PPIs to a register */\n+ uint64_t ppi_priority[GICV5_NUM_PPIS / 8];\n } gicv5_cpuif;\n \n struct {\ndiff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 09cd56cbfa..74132ca097 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -225,6 +225,12 @@ static void gic_ppi_enable_write(CPUARMState *env, const ARMCPRegInfo *ri,\n raw_write(env, ri, value);\n }\n \n+static void gic_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ raw_write(env, ri, value);\n+}\n+\n static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n /*\n * Barrier: wait until the effects of a cpuif system register\n@@ -382,5 +388,22 @@ void define_gicv5_cpuif_regs(ARMCPU *cpu)\n {\n if (cpu_isar_feature(aa64_gcie, cpu)) {\n define_arm_cp_regs(cpu, gicv5_cpuif_reginfo);\n+\n+ /*\n+ * There are 16 ICC_PPI_PRIORITYR<n>_EL1 regs, so define them\n+ * programmatically rather than listing them all statically.\n+ */\n+ for (int i = 0; i < 16; i++) {\n+ g_autofree char *name = g_strdup_printf(\"ICC_PPI_PRIORITYR%d_EL1\", i);\n+ ARMCPRegInfo ppi_prio = {\n+ .name = name, .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 0, .crn = 12,\n+ .crm = 14 + (i >> 3), .opc2 = i & 7,\n+ .access = PL1_RW, .type = ARM_CP_IO,\n+ .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_priority[i]),\n+ .writefn = gic_ppi_priority_write, .raw_writefn = raw_write,\n+ };\n+ define_one_arm_cp_reg(cpu, &ppi_prio);\n+ }\n }\n }\n", "prefixes": [ "v2", "40/65" ] }