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GET /api/patches/2216922/?format=api
{ "id": 2216922, "url": "http://patchwork.ozlabs.org/api/patches/2216922/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-10-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-10-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:04", "name": "[v2,09/65] hw/intc/arm_gicv5: Define macros for config frame registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ff714543478e3b0c50127c27718cd27c184204ec", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-10-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216922/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216922/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ENlt1IT/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhywp0HsJz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:24:58 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Bq-0006UR-5V; Fri, 27 Mar 2026 07:17:22 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bj-0006Pd-Cj\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:15 -0400", "from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bh-0007m3-2q\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:14 -0400", "by mail-wr1-x42c.google.com with SMTP id\n ffacd0b85a97d-439b9b190easo1387289f8f.2\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:12 -0700 (PDT)", "from lanath.. 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"Date": "Fri, 27 Mar 2026 11:16:04 +0000", "Message-ID": "<20260327111700.795099-10-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327111700.795099-1-peter.maydell@linaro.org>", "References": "<20260327111700.795099-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::42c;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Define constants for the various registers in the IRS config frame\nusing the REG and FIELD macros.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5.c | 243 ++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 243 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex cb1234b022..4c1ec8f30a 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -7,6 +7,7 @@\n */\n \n #include \"qemu/osdep.h\"\n+#include \"hw/core/registerfields.h\"\n #include \"hw/intc/arm_gicv5.h\"\n #include \"qapi/error.h\"\n #include \"qemu/log.h\"\n@@ -22,6 +23,248 @@ static const char *domain_name[] = {\n [GICV5_ID_REALM] = \"Realm\",\n };\n \n+REG32(IRS_IDR0, 0x0)\n+ FIELD(IRS_IDR0, INT_DOM, 0, 2)\n+ FIELD(IRS_IDR0, PA_RANGE, 2, 4)\n+ FIELD(IRS_IDR0, VIRT, 6, 1)\n+ FIELD(IRS_IDR0, ONE_N, 7, 1)\n+ FIELD(IRS_IDR0, VIRT_ONE_N, 8, 1)\n+ FIELD(IRS_IDR0, SETLPI, 9, 1)\n+ FIELD(IRS_IDR0, MEC, 10, 1)\n+ FIELD(IRS_IDR0, MPAM, 11, 1)\n+ FIELD(IRS_IDR0, SWE, 12, 1)\n+ FIELD(IRS_IDR0, IRSID, 16, 16)\n+\n+REG32(IRS_IDR1, 0x4)\n+ FIELD(IRS_IDR1, PE_CNT, 0, 16)\n+ FIELD(IRS_IDR1, IAFFID_BITS, 16, 4)\n+ FIELD(IRS_IDR1, PRI_BITS, 20, 3)\n+\n+REG32(IRS_IDR2, 0x8)\n+ FIELD(IRS_IDR2, ID_BITS, 0, 5)\n+ FIELD(IRS_IDR2, LPI, 5, 1)\n+ FIELD(IRS_IDR2, MIN_LPI_ID_BITS, 6, 4)\n+ FIELD(IRS_IDR2, IST_LEVELS, 10, 1)\n+ FIELD(IRS_IDR2, IST_L2SZ, 11, 3)\n+ FIELD(IRS_IDR2, IST_MD, 14, 1)\n+ FIELD(IRS_IDR2, ISTMD_SZ, 15, 5)\n+\n+REG32(IRS_IDR3, 0xc)\n+ FIELD(IRS_IDR3, VMD, 0, 1)\n+ FIELD(IRS_IDR3, VMD_SZ, 1, 4)\n+ FIELD(IRS_IDR3, VM_ID_BITS, 5, 5)\n+ FIELD(IRS_IDR3, VMT_LEVELS, 10, 1)\n+\n+REG32(IRS_IDR4, 0x10)\n+ FIELD(IRS_IDR4, VPED_SZ, 0, 6)\n+ FIELD(IRS_IDR4, VPE_ID_BITS, 6, 4)\n+\n+REG32(IRS_IDR5, 0x14)\n+ FIELD(IRS_IDR5, SPI_RANGE, 0, 25)\n+\n+REG32(IRS_IDR6, 0x18)\n+ FIELD(IRS_IDR6, SPI_IRS_RANGE, 0, 25)\n+\n+REG32(IRS_IDR7, 0x1c)\n+ FIELD(IRS_IDR7, SPI_BASE, 0, 24)\n+\n+REG32(IRS_IIDR, 0x40)\n+ FIELD(IRS_IIDR, IMPLEMENTER, 0, 12)\n+ FIELD(IRS_IIDR, REVISION, 12, 4)\n+ FIELD(IRS_IIDR, VARIANT, 16, 4)\n+ FIELD(IRS_IIDR, PRODUCTID, 20, 12)\n+\n+REG32(IRS_AIDR, 0x44)\n+ FIELD(IRS_AIDR, ARCHMINORREV, 0, 4)\n+ FIELD(IRS_AIDR, ARCHMAJORREV, 4, 4)\n+ FIELD(IRS_AIDR, COMPONENT, 8, 4)\n+\n+REG32(IRS_CR0, 0x80)\n+ FIELD(IRS_CR0, IRSEN, 0, 1)\n+ FIELD(IRS_CR0, IDLE, 1, 1)\n+\n+REG32(IRS_CR1, 0x84)\n+ FIELD(IRS_CR1, SH, 0, 2)\n+ FIELD(IRS_CR1, OC, 2, 2)\n+ FIELD(IRS_CR1, IC, 4, 2)\n+ FIELD(IRS_CR1, IST_RA, 6, 1)\n+ FIELD(IRS_CR1, IST_WA, 7, 1)\n+ FIELD(IRS_CR1, VMT_RA, 8, 1)\n+ FIELD(IRS_CR1, VMT_WA, 9, 1)\n+ FIELD(IRS_CR1, VPET_RA, 10, 1)\n+ FIELD(IRS_CR1, VPET_WA, 11, 1)\n+ FIELD(IRS_CR1, VMD_RA, 12, 1)\n+ FIELD(IRS_CR1, VMD_WA, 13, 1)\n+ FIELD(IRS_CR1, VPED_RA, 14, 1)\n+ FIELD(IRS_CR1, VPED_WA, 15, 1)\n+\n+REG32(IRS_SYNCR, 0xc0)\n+ FIELD(IRS_SYNCR, SYNC, 31, 1)\n+\n+REG32(IRS_SYNC_STATUSR, 0xc4)\n+ FIELD(IRS_SYNC_STATUSR, IDLE, 0, 1)\n+\n+REG64(IRS_SPI_VMR, 0x100)\n+ FIELD(IRS_SPI_VMR, VM_ID, 0, 16)\n+ FIELD(IRS_SPI_VMR, VIRT, 63, 1)\n+\n+REG32(IRS_SPI_SELR, 0x108)\n+ FIELD(IRS_SPI_SELR, ID, 0, 24)\n+\n+REG32(IRS_SPI_DOMAINR, 0x10c)\n+ FIELD(IRS_SPI_DOMAINR, DOMAIN, 0, 2)\n+\n+REG32(IRS_SPI_RESAMPLER, 0x110)\n+ FIELD(IRS_SPI_RESAMPLER, SPI_ID, 0, 24)\n+\n+REG32(IRS_SPI_CFGR, 0x114)\n+ FIELD(IRS_SPI_CFGR, TM, 0, 1)\n+\n+REG32(IRS_SPI_STATUSR, 0x118)\n+ FIELD(IRS_SPI_STATUSR, IDLE, 0, 1)\n+ FIELD(IRS_SPI_STATUSR, V, 1, 1)\n+\n+REG32(IRS_PE_SELR, 0x140)\n+ FIELD(IRS_PE_SELR, IAFFID, 0, 16)\n+\n+REG32(IRS_PE_STATUSR, 0x144)\n+ FIELD(IRS_PE_STATUSR, IDLE, 0, 1)\n+ FIELD(IRS_PE_STATUSR, V, 1, 1)\n+ FIELD(IRS_PE_STATUSR, ONLINE, 2, 1)\n+\n+REG32(IRS_PE_CR0, 0x148)\n+ FIELD(IRS_PE_CR0, DPS, 0, 1)\n+\n+REG64(IRS_IST_BASER, 0x180)\n+ FIELD(IRS_IST_BASER, VALID, 0, 1)\n+ FIELD(IRS_IST_BASER, ADDR, 6, 50)\n+\n+REG32(IRS_IST_CFGR, 0x190)\n+ FIELD(IRS_IST_CFGR, LPI_ID_BITS, 0, 5)\n+ FIELD(IRS_IST_CFGR, L2SZ, 5, 2)\n+ FIELD(IRS_IST_CFGR, ISTSZ, 7, 2)\n+ FIELD(IRS_IST_CFGR, STRUCTURE, 16, 1)\n+\n+REG32(IRS_IST_STATUSR, 0x194)\n+ FIELD(IRS_IST_STATUSR, IDLE, 0, 1)\n+\n+REG32(IRS_MAP_L2_ISTR, 0x1c0)\n+ FIELD(IRS_MAP_L2_ISTR, ID, 0, 24)\n+\n+REG64(IRS_VMT_BASER, 0x200)\n+ FIELD(IRS_VMT_BASER, VALID, 0, 1)\n+ FIELD(IRS_VMT_BASER, ADDR, 3, 53)\n+\n+REG32(IRS_VMT_CFGR, 0x210)\n+ FIELD(IRS_VMT_CFGR, VM_ID_BITS, 0, 5)\n+ FIELD(IRS_VMT_CFGR, STRUCTURE, 16, 1)\n+\n+REG32(IRS_VMT_STATUSR, 0x124)\n+ FIELD(IRS_VMT_STATUSR, IDLE, 0, 1)\n+\n+REG64(IRS_VPE_SELR, 0x240)\n+ FIELD(IRS_VPE_SELR, VM_ID, 0, 16)\n+ FIELD(IRS_VPE_SELR, VPE_ID, 32, 16)\n+ FIELD(IRS_VPE_SELR, S, 63, 1)\n+\n+REG64(IRS_VPE_DBR, 0x248)\n+ FIELD(IRS_VPE_DBR, INTID, 0, 24)\n+ FIELD(IRS_VPE_DBR, DBPM, 32, 5)\n+ FIELD(IRS_VPE_DBR, REQ_DB, 62, 1)\n+ FIELD(IRS_VPE_DBR, DBV, 63, 1)\n+\n+REG32(IRS_VPE_HPPIR, 0x250)\n+ FIELD(IRS_VPE_HPPIR, ID, 0, 24)\n+ FIELD(IRS_VPE_HPPIR, TYPE, 29, 3)\n+ FIELD(IRS_VPE_HPPIR, HPPIV, 32, 1)\n+\n+REG32(IRS_VPE_CR0, 0x258)\n+ FIELD(IRS_VPE_CR0, DPS, 0, 1)\n+\n+REG32(IRS_VPE_STATUSR, 0x25c)\n+ FIELD(IRS_VPE_STATUSR, IDLE, 0, 1)\n+ FIELD(IRS_VPE_STATUSR, V, 1, 1)\n+\n+REG64(IRS_VM_DBR, 0x280)\n+ FIELD(IRS_VM_DBR, VPE_ID, 0, 16)\n+ FIELD(IRS_VM_DBR, EN, 63, 1)\n+\n+REG32(IRS_VM_SELR, 0x288)\n+ FIELD(IRS_VM_SELR, VM_ID, 0, 16)\n+\n+REG32(IRS_VM_STATUSR, 0x28c)\n+ FIELD(IRS_VM_STATUSR, IDLE, 0, 1)\n+ FIELD(IRS_VM_STATUSR, V, 1, 1)\n+\n+REG64(IRS_VMAP_L2_VMTR, 0x2c0)\n+ FIELD(IRS_VMAP_L2_VMTR, VM_ID, 0, 16)\n+ FIELD(IRS_VMAP_L2_VMTR, M, 63, 1)\n+\n+REG64(IRS_VMAP_VMR, 0x2c8)\n+ FIELD(IRS_VMAP_VMR, VM_ID, 0, 16)\n+ FIELD(IRS_VMAP_VMR, U, 62, 1)\n+ FIELD(IRS_VMAP_VMR, M, 63, 1)\n+\n+REG64(IRS_VMAP_VISTR, 0x2d0)\n+ FIELD(IRS_VMAP_VISTR, TYPE, 29, 3)\n+ FIELD(IRS_VMAP_VISTR, VM_ID, 32, 16)\n+ FIELD(IRS_VMAP_VISTR, U, 62, 1)\n+ FIELD(IRS_VMAP_VISTR, M, 63, 1)\n+\n+REG64(IRS_VMAP_L2_VISTR, 0x2d8)\n+ FIELD(IRS_VMAP_L2_VISTR, ID, 0, 24)\n+ FIELD(IRS_VMAP_L2_VISTR, TYPE, 29, 3)\n+ FIELD(IRS_VMAP_L2_VISTR, VM_ID, 32, 16)\n+ FIELD(IRS_VMAP_L2_VISTR, M, 63, 1)\n+\n+REG64(IRS_VMAP_VPER, 0x2e0)\n+ FIELD(IRS_VMAP_VPER, VPE_ID, 0, 16)\n+ FIELD(IRS_VMAP_VPER, VM_ID, 32, 16)\n+ FIELD(IRS_VMAP_VPER, M, 63, 1)\n+\n+REG64(IRS_SAVE_VMR, 0x300)\n+ FIELD(IRS_SAVE_VMR, VM_ID, 0, 16)\n+ FIELD(IRS_SAVE_VMR, Q, 62, 1)\n+ FIELD(IRS_SAVE_VMR, S, 63, 1)\n+\n+REG32(IRS_SAVE_VM_STATUSR, 0x308)\n+ FIELD(IRS_SAVE_VM_STATUSR, IDLE, 0, 1)\n+ FIELD(IRS_SAVE_VM_STATUSR, Q, 1, 1)\n+\n+REG32(IRS_MEC_IDR, 0x340)\n+ FIELD(IRS_MEC_IDR, MECIDSIZE, 0, 4)\n+\n+REG32(IRS_MEC_MECID_R, 0x344)\n+ FIELD(IRS_MEC_MICID_R, MECID, 0, 16)\n+\n+REG32(IRS_MPAM_IDR, 0x380)\n+ FIELD(IRS_MPAM_IDR, PARTID_MAX, 0, 16)\n+ FIELD(IRS_MPAM_IDR, PMG_MAX, 16, 8)\n+ FIELD(IRS_MPAM_IDR, HAS_MPAM_SP, 24, 1)\n+\n+REG32(IRS_MPAM_PARTID_R, 0x384)\n+ FIELD(IRS_MPAM_IDR, PARTID, 0, 16)\n+ FIELD(IRS_MPAM_IDR, PMG, 16, 8)\n+ FIELD(IRS_MPAM_IDR, MPAM_SP, 24, 2)\n+ FIELD(IRS_MPAM_IDR, IDLE, 31, 1)\n+\n+REG64(IRS_SWERR_STATUSR, 0x3c0)\n+ FIELD(IRS_SWERR_STATUSR, V, 0, 1)\n+ FIELD(IRS_SWERR_STATUSR, S0V, 1, 1)\n+ FIELD(IRS_SWERR_STATUSR, S1V, 2, 1)\n+ FIELD(IRS_SWERR_STATUSR, OF, 3, 1)\n+ FIELD(IRS_SWERR_STATUSR, EC, 16, 8)\n+ FIELD(IRS_SWERR_STATUSR, IMP_EC, 24, 8)\n+\n+REG64(IRS_SWERR_SYNDROMER0, 0x3c8)\n+ FIELD(IRS_SWERR_SYNDROMER0, VM_ID, 0, 16)\n+ FIELD(IRS_SWERR_SYNDROMER0, ID, 32, 24)\n+ FIELD(IRS_SWERR_SYNDROMER0, TYPE, 60, 3)\n+ FIELD(IRS_SWERR_SYNDROMER0, VIRTUAL, 63, 1)\n+\n+REG64(IRS_SWERR_SYNDROMER1, 0x3d0)\n+ FIELD(IRS_SWERR_SYNDROMER2, ADDR, 3, 53)\n+\n static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,\n uint64_t *data, MemTxAttrs attrs)\n {\n", "prefixes": [ "v2", "09/65" ] }