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GET /api/patches/2216906/?format=api
{ "id": 2216906, "url": "http://patchwork.ozlabs.org/api/patches/2216906/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-32-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-32-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:26", "name": "[v2,31/65] hw/intc/arm_gicv5: Implement IRS_PE_{CR0, SELR, STATUSR}", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b4ae4b37e16c6320d1df122728d72b4f1f381f79", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-32-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216906/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216906/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=HD2Rk4VL;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhytH0gVKz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:22:47 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65CE-00072g-Er; Fri, 27 Mar 2026 07:17:46 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C3-0006nl-DT\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:35 -0400", "from mail-wm1-x329.google.com ([2a00:1450:4864:20::329])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C1-000822-4T\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:35 -0400", "by mail-wm1-x329.google.com with SMTP id\n 5b1f17b1804b1-486fb14227cso24721415e9.3\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:32 -0700 (PDT)", "from lanath.. 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Software writes the AFFID of a CPU\nto IRS_PE_SELR, and can then read and write the 1ofN config for that\nCPU to IRS_PE_CR0, and read the CPU's online status from\nIRS_PE_STATUSR.\n\nFor QEMU, we do not implement 1-of-N interrupt routing, so IRS_PE_CR0\ncan be RAZ/WI. Our CPUs are always online and selecting a new one\nvia SELR is instantaneous, so IRS_PE_STATUSR will return either\nONLINE | V | IDLE if a valid AFFID was written to SELR, or just IDLE\nif an invalid AFFID was written.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5.c | 39 ++++++++++++++++++++++++++++++\n hw/intc/arm_gicv5_common.c | 1 +\n include/hw/intc/arm_gicv5_common.h | 1 +\n 3 files changed, 41 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex 7b0d9e16c4..a95a9dc16b 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -968,6 +968,21 @@ static void spi_sample(GICv5SPIState *spi)\n }\n }\n \n+static bool irs_pe_selr_valid(GICv5Common *cs, GICv5Domain domain)\n+{\n+ /*\n+ * Return true if IRS_PE_SELR has a valid AFFID in it. We don't\n+ * expect the guest to do this except perhaps once at startup, so\n+ * do a simple linear scan through the cpu_iaffids array.\n+ */\n+ for (int i = 0; i < cs->num_cpu_iaffids; i++) {\n+ if (cs->irs_pe_selr[domain] == cs->cpu_iaffids[i]) {\n+ return true;\n+ }\n+ }\n+ return false;\n+}\n+\n static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,\n uint64_t *data, MemTxAttrs attrs)\n {\n@@ -1091,6 +1106,24 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,\n /* Sync is a no-op for QEMU: we are always IDLE */\n *data = R_IRS_SYNC_STATUSR_IDLE_MASK;\n return true;\n+ case A_IRS_PE_SELR:\n+ *data = cs->irs_pe_selr[domain];\n+ return true;\n+ case A_IRS_PE_CR0:\n+ /* We don't implement 1ofN, so this is RAZ/WI for us */\n+ *data = 0;\n+ return true;\n+ case A_IRS_PE_STATUSR:\n+ /*\n+ * Our CPUs are always online, so we're really just reporting\n+ * whether the guest wrote a valid AFFID to IRS_PE_SELR\n+ */\n+ v = R_IRS_PE_STATUSR_IDLE_MASK;\n+ if (irs_pe_selr_valid(cs, domain)) {\n+ v |= R_IRS_PE_STATUSR_V_MASK | R_IRS_PE_STATUSR_ONLINE_MASK;\n+ }\n+ *data = v;\n+ return true;\n }\n \n return false;\n@@ -1179,6 +1212,12 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset,\n case A_IRS_SYNCR:\n /* Sync is a no-op for QEMU: ignore write */\n return true;\n+ case A_IRS_PE_SELR:\n+ cs->irs_pe_selr[domain] = data;\n+ return true;\n+ case A_IRS_PE_CR0:\n+ /* We don't implement 1ofN, so this is RAZ/WI for us */\n+ return true;\n }\n \n return false;\ndiff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c\nindex b1c8ec4521..5510e6239a 100644\n--- a/hw/intc/arm_gicv5_common.c\n+++ b/hw/intc/arm_gicv5_common.c\n@@ -68,6 +68,7 @@ static void gicv5_common_reset_hold(Object *obj, ResetType type)\n memset(cs->irs_ist_cfgr, 0, sizeof(cs->irs_ist_cfgr));\n memset(cs->irs_cr0, 0, sizeof(cs->irs_cr0));\n memset(cs->irs_cr1, 0, sizeof(cs->irs_cr1));\n+ memset(cs->irs_pe_selr, 0, sizeof(cs->irs_pe_selr));\n \n if (cs->spi) {\n GICv5Domain mp_domain;\ndiff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5_common.h\nindex ac0532abe8..34ad38c198 100644\n--- a/include/hw/intc/arm_gicv5_common.h\n+++ b/include/hw/intc/arm_gicv5_common.h\n@@ -86,6 +86,7 @@ struct GICv5Common {\n uint32_t irs_spi_selr[NUM_GICV5_DOMAINS];\n uint32_t irs_cr0[NUM_GICV5_DOMAINS];\n uint32_t irs_cr1[NUM_GICV5_DOMAINS];\n+ uint32_t irs_pe_selr[NUM_GICV5_DOMAINS];\n \n /*\n * Pointer to an array of state information for the SPIs. Array\n", "prefixes": [ "v2", "31/65" ] }