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GET /api/patches/2216873/?format=api
{ "id": 2216873, "url": "http://patchwork.ozlabs.org/api/patches/2216873/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-29-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-29-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:23", "name": "[v2,28/65] hw/intc/arm_gicv5: Update SPI state for CLEAR/SET events", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "00903392778695887bf9e1c3ad60fa680618052f", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-29-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216873/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216873/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=wfEpRQj4;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhymp4ZTYz1y1x\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:18:02 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65C4-0006oj-BJ; Fri, 27 Mar 2026 07:17:36 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C0-0006jt-Sn\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:32 -0400", "from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65By-00080U-Nu\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:32 -0400", "by mail-wr1-x42f.google.com with SMTP id\n ffacd0b85a97d-43b8982c2f4so1121578f8f.2\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:30 -0700 (PDT)", "from lanath.. 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These also happen\nwhen the trigger mode is reconfigured, or when software requests a\nmanual resample via the IRS_SPI_RESAMPLER register.\n\nSET_LEVEL and SET_EDGE events make the interrupt pending, and update\nits handler mode to match its trigger mode. CLEAR events make the\ninterrupt no longer pending.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5.c | 59 ++++++++++++++++++++++++++++++++++++++++++++\n hw/intc/trace-events | 1 +\n 2 files changed, 60 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex 6ff3a79745..bc887233f5 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -946,6 +946,28 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t value)\n }\n }\n \n+static void spi_sample(GICv5SPIState *spi)\n+{\n+ /*\n+ * Sample the state of the SPI input line; this generates\n+ * SET_EDGE, SET_LEVEL or CLEAR events which update the SPI's\n+ * pending state and handling mode per R_HHKMN. The logic is the\n+ * same for \"the input line changed\" (R_QBXXV) and \"software asked\n+ * us to resample\" (R_DMTFM).\n+ */\n+ if (spi->level) {\n+ /*\n+ * SET_LEVEL or SET_EDGE: interrupt becomes pending, and the\n+ * handling mode is updated to match the trigger mode.\n+ */\n+ spi->pending = true;\n+ spi->hm = spi->tm == GICV5_TRIGGER_EDGE ? GICV5_EDGE : GICV5_LEVEL;\n+ } else if (spi->tm == GICV5_TRIGGER_LEVEL) {\n+ /* falling edges only trigger a CLEAR event for level-triggered */\n+ spi->pending = false;\n+ }\n+}\n+\n static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,\n uint64_t *data, MemTxAttrs attrs)\n {\n@@ -1096,7 +1118,24 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset,\n {\n GICv5SPIState *spi = spi_for_selr(cs, domain);\n if (spi) {\n+ GICv5TriggerMode old_tm = spi->tm;\n spi->tm = FIELD_EX32(data, IRS_SPI_CFGR, TM);\n+ if (spi->tm != old_tm) {\n+ /*\n+ * R_KBPXL: updates to SPI trigger mode can generate CLEAR or\n+ * SET_LEVEL events. This is not the same logic as spi_sample().\n+ */\n+ if (spi->tm == GICV5_TRIGGER_LEVEL) {\n+ if (spi->level) {\n+ spi->pending = true;\n+ spi->hm = GICV5_LEVEL;\n+ } else {\n+ spi->pending = false;\n+ }\n+ } else if (spi->level) {\n+ spi->pending = false;\n+ }\n+ }\n }\n return true;\n }\n@@ -1109,6 +1148,17 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset,\n }\n }\n return true;\n+ case A_IRS_SPI_RESAMPLER:\n+ {\n+ uint32_t id = FIELD_EX32(data, IRS_SPI_RESAMPLER, SPI_ID);\n+ GICv5SPIState *spi = gicv5_spi_state(cs, id, domain);\n+\n+ if (spi) {\n+ spi_sample(spi);\n+ }\n+ trace_gicv5_spi_state(id, spi->level, spi->pending, spi->active);\n+ return true;\n+ }\n }\n \n return false;\n@@ -1259,8 +1309,17 @@ static void gicv5_set_spi(void *opaque, int irq, int level)\n /* These irqs are all SPIs; the INTID is irq + s->spi_base */\n GICv5Common *cs = ARM_GICV5_COMMON(opaque);\n uint32_t spi_id = irq + cs->spi_base;\n+ GICv5SPIState *spi = gicv5_raw_spi_state(cs, spi_id);\n+\n+ if (!spi || spi->level == level) {\n+ return;\n+ }\n \n trace_gicv5_spi(spi_id, level);\n+\n+ spi->level = level;\n+ spi_sample(spi);\n+ trace_gicv5_spi_state(spi_id, spi->level, spi->pending, spi->active);\n }\n \n static void gicv5_reset_hold(Object *obj, ResetType type)\ndiff --git a/hw/intc/trace-events b/hw/intc/trace-events\nindex 409935e15a..4c55af2780 100644\n--- a/hw/intc/trace-events\n+++ b/hw/intc/trace-events\n@@ -241,6 +241,7 @@ gicv5_set_pending(const char *domain, const char *type, bool virtual, uint32_t i\n gicv5_set_handling(const char *domain, const char *type, bool virtual, uint32_t id, int handling) \"GICv5 IRS SetHandling %s %s virtual:%d ID %u handling %d\"\n gicv5_set_target(const char *domain, const char *type, bool virtual, uint32_t id, uint32_t iaffid, int irm) \"GICv5 IRS SetTarget %s %s virtual:%d ID %u IAFFID %u routingmode %d\"\n gicv5_request_config(const char *domain, const char *type, bool virtual, uint32_t id, uint64_t icsr) \"GICv5 IRS RequestConfig %s %s virtual:%d ID %u ICSR 0x%\" PRIx64\n+gicv5_spi_state(uint32_t spi_id, bool level, bool pending, bool active) \"GICv5 IRS SPI ID %u now level %d pending %d active %d\"\n \n # arm_gicv5_common.c\n gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base, uint32_t spi_irs_range, uint32_t spi_range) \"GICv5 IRS realized: IRS ID %u, %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u\"\n", "prefixes": [ "v2", "28/65" ] }