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GET /api/patches/2216899/?format=api
{ "id": 2216899, "url": "http://patchwork.ozlabs.org/api/patches/2216899/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-28-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-28-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:22", "name": "[v2,27/65] hw/intc/arm_gicv5: Implement IRS_SPI_{SELR, STATUSR, CFGR, DOMAINR}", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9199d9d68a67ea26a72a9f22687e0c7d0d8bbf0c", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-28-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216899/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216899/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Ep18Gnv7;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhysG2Zq9z1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:21:54 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65C4-0006og-8E; Fri, 27 Mar 2026 07:17:36 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C0-0006it-As\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:32 -0400", "from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65By-0007zV-Ch\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:32 -0400", "by mail-wm1-x32d.google.com with SMTP id\n 5b1f17b1804b1-486fc4725f0so17971895e9.1\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:29 -0700 (PDT)", "from lanath.. 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The way these work is that the guest writes the ID of the\ninterrupt it wants to configure to IRS_SPI_SELR, and then it can read\nand write the trigger mode of that SPI via IRS_SPI_CFGR and the\ndomain via IRS_SPI_DOMAINR. IRS_SPI_STATUSR has a bit to indicate\nwhether the SPI is valid, and the usual IDLE bit to allow for\nnon-instantaneous updates (which QEMU doesn't do).\n\nSince the only domain which can configure the domain of an SPI is EL3\nand our initial implementation is NS-only, technically the DOMAINR\nhandling is unused code. However it is straightforward, being almost\nthe same as the CFGR handling, and we'll need it later on.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5.c | 68 ++++++++++++++++++++++++++++++\n hw/intc/arm_gicv5_common.c | 9 ++++\n include/hw/intc/arm_gicv5_common.h | 1 +\n 3 files changed, 78 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex 04d4391ae5..6ff3a79745 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -310,6 +310,22 @@ FIELD(ICSR, HM, 5, 1)\n FIELD(ICSR, PRIORITY, 11, 5)\n FIELD(ICSR, IAFFID, 32, 16)\n \n+static GICv5SPIState *spi_for_selr(GICv5Common *cs, GICv5Domain domain)\n+{\n+ /*\n+ * If the IRS_SPI_SELR value specifies an SPI that can be managed in\n+ * this domain, return a pointer to its GICv5SPIState; otherwise\n+ * return NULL.\n+ */\n+ uint32_t id = FIELD_EX32(cs->irs_spi_selr[domain], IRS_SPI_SELR, ID);\n+ GICv5SPIState *spi = gicv5_raw_spi_state(cs, id);\n+\n+ if (spi && (domain == GICV5_ID_EL3 || domain == spi->domain)) {\n+ return spi;\n+ }\n+ return NULL;\n+}\n+\n static MemTxAttrs irs_txattrs(GICv5Common *cs, GICv5Domain domain)\n {\n /*\n@@ -1010,6 +1026,38 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,\n case A_IRS_IST_CFGR:\n *data = cs->irs_ist_cfgr[domain];\n return true;\n+\n+ case A_IRS_SPI_STATUSR:\n+ /*\n+ * QEMU writes to IRS_SPI_{CFGR,DOMAINR,SELR,VMR} take effect\n+ * instantaneously, so the guest can never see the IDLE bit as 0.\n+ */\n+ v = FIELD_DP32(v, IRS_SPI_STATUSR, V,\n+ spi_for_selr(cs, domain) != NULL);\n+ v = FIELD_DP32(v, IRS_SPI_STATUSR, IDLE, 1);\n+ *data = v;\n+ return true;\n+\n+ case A_IRS_SPI_CFGR:\n+ {\n+ GICv5SPIState *spi = spi_for_selr(cs, domain);\n+\n+ if (spi) {\n+ v = FIELD_DP32(v, IRS_SPI_CFGR, TM, spi->tm);\n+ }\n+ *data = v;\n+ return true;\n+ }\n+ case A_IRS_SPI_DOMAINR:\n+ if (domain == GICV5_ID_EL3) {\n+ /* This is RAZ/WI except for the EL3 domain */\n+ GICv5SPIState *spi = spi_for_selr(cs, domain);\n+ if (spi) {\n+ v = FIELD_DP32(v, IRS_SPI_DOMAINR, DOMAIN, spi->domain);\n+ }\n+ }\n+ *data = v;\n+ return true;\n }\n \n return false;\n@@ -1041,6 +1089,26 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset,\n case A_IRS_MAP_L2_ISTR:\n irs_map_l2_istr_write(s, domain, data);\n return true;\n+ case A_IRS_SPI_SELR:\n+ cs->irs_spi_selr[domain] = data;\n+ return true;\n+ case A_IRS_SPI_CFGR:\n+ {\n+ GICv5SPIState *spi = spi_for_selr(cs, domain);\n+ if (spi) {\n+ spi->tm = FIELD_EX32(data, IRS_SPI_CFGR, TM);\n+ }\n+ return true;\n+ }\n+ case A_IRS_SPI_DOMAINR:\n+ if (domain == GICV5_ID_EL3) {\n+ /* this is RAZ/WI except for the EL3 domain */\n+ GICv5SPIState *spi = spi_for_selr(cs, domain);\n+ if (spi) {\n+ spi->domain = FIELD_EX32(data, IRS_SPI_DOMAINR, DOMAIN);\n+ }\n+ }\n+ return true;\n }\n \n return false;\ndiff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c\nindex 79876c4401..0813f0ac66 100644\n--- a/hw/intc/arm_gicv5_common.c\n+++ b/hw/intc/arm_gicv5_common.c\n@@ -94,6 +94,15 @@ static void gicv5_common_reset_hold(Object *obj, ResetType type)\n cs->spi[i].domain = mp_domain;\n }\n }\n+\n+ for (int i = 0; i < NUM_GICV5_DOMAINS; i++) {\n+ /*\n+ * We reset irs_spi_selr to an invalid value so that our reset\n+ * value for IRS_SPI_STATUSR.V is correctly 0. The guest can\n+ * never read IRS_SPI_SELR directly.\n+ */\n+ cs->irs_spi_selr[i] = cs->spi_base + cs->spi_irs_range;\n+ }\n }\n \n static void gicv5_common_init(Object *obj)\ndiff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5_common.h\nindex a81c941765..61d017bf38 100644\n--- a/include/hw/intc/arm_gicv5_common.h\n+++ b/include/hw/intc/arm_gicv5_common.h\n@@ -83,6 +83,7 @@ struct GICv5Common {\n \n uint64_t irs_ist_baser[NUM_GICV5_DOMAINS];\n uint32_t irs_ist_cfgr[NUM_GICV5_DOMAINS];\n+ uint32_t irs_spi_selr[NUM_GICV5_DOMAINS];\n \n /*\n * Pointer to an array of state information for the SPIs. Array\n", "prefixes": [ "v2", "27/65" ] }