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GET /api/patches/2216874/?format=api
{ "id": 2216874, "url": "http://patchwork.ozlabs.org/api/patches/2216874/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-35-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-35-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:29", "name": "[v2,34/65] target/arm: GICv5 cpuif: Implement ICC_IAFFIDR_EL1", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f5ba15f3b3b964515bf5056ba2973121daf5f343", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-35-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216874/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216874/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=A4in92nW;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhymy1NPdz1y1x\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:18:10 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65C9-0006wO-FJ; Fri, 27 Mar 2026 07:17:41 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C6-0006sm-U0\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:38 -0400", "from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C4-000880-EC\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:38 -0400", "by mail-wr1-x42f.google.com with SMTP id\n ffacd0b85a97d-439b9cf8cb5so1919286f8f.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:35 -0700 (PDT)", "from lanath.. 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In real hardware using the stream protocol,\nthe IRS tells the CPU its IAFFID using a DownstreamControl command as\npart of the handshake process when the IRS-CPU link is brought\nonline. Our analogue of this is to pass the IAFFID as an extra\nargument to gicv5_set_gicv5state(). (We could have the CPU call into\nthe GIC every time to ask for the value, but this would mean we had\nto search the cpus[] array for the right CPU to return its IAFFID.)\n\nNote that we don't put the IAFFID into the gicv5_cpuif sub-struct,\nbecause that part of the CPU struct is zeroed on reset, and we must\nkeep the IAFFID across reset (we only set it up when the GIC device\nis created).\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5_common.c | 5 +++--\n include/hw/intc/arm_gicv5_stream.h | 3 ++-\n target/arm/cpu.c | 5 +++--\n target/arm/cpu.h | 2 ++\n target/arm/tcg/gicv5-cpuif.c | 11 +++++++++++\n 5 files changed, 21 insertions(+), 5 deletions(-)", "diff": "diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c\nindex 5510e6239a..0b5303f370 100644\n--- a/hw/intc/arm_gicv5_common.c\n+++ b/hw/intc/arm_gicv5_common.c\n@@ -175,9 +175,10 @@ static void gicv5_common_realize(DeviceState *dev, Error **errp)\n }\n \n for (int i = 0; i < cs->num_cpus; i++) {\n- if (!gicv5_set_gicv5state(cs->cpus[i], cs)) {\n+ if (!gicv5_set_gicv5state(cs->cpus[i], cs, cs->cpu_iaffids[i])) {\n error_setg(errp,\n- \"CPU %d does not implement GICv5 CPU interface\", i);\n+ \"CPU %d (IAFFID 0x%x) does not implement GICv5 CPU interface\",\n+ i, cs->cpu_iaffids[i]);\n return;\n }\n }\ndiff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5_stream.h\nindex 670423fdad..136b6339ee 100644\n--- a/include/hw/intc/arm_gicv5_stream.h\n+++ b/include/hw/intc/arm_gicv5_stream.h\n@@ -20,6 +20,7 @@ typedef struct GICv5Common GICv5Common;\n * gicv5_set_gicv5state\n * @cpu: CPU object to tell about its IRS\n * @cs: the GIC IRS it is connected to\n+ * @iaffid: the IAFFID of this CPU\n *\n * Set the CPU object's GICv5 pointer to point to this GIC IRS. The\n * IRS must call this when it is realized, for each CPU it is\n@@ -28,7 +29,7 @@ typedef struct GICv5Common GICv5Common;\n * Returns true on success, false if the CPU doesn't implement the\n * GICv5 CPU interface.\n */\n-bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs);\n+bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs, uint32_t iaffid);\n \n /*\n * The architected Stream Protocol is asynchronous; commands can be\ndiff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex 4044bce5b6..ceb303a55a 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -1087,16 +1087,17 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)\n }\n \n #ifndef CONFIG_USER_ONLY\n-bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs)\n+bool gicv5_set_gicv5state(ARMCPU *cpu, GICv5Common *cs, uint32_t iaffid)\n {\n /*\n * Set this CPU's gicv5state pointer to point to the GIC that we are\n- * connected to.\n+ * connected to, and record our IAFFID.\n */\n if (!cpu_isar_feature(aa64_gcie, cpu)) {\n return false;\n }\n cpu->env.gicv5state = cs;\n+ cpu->env.gicv5_iaffid = iaffid;\n return true;\n }\n #endif\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 1fdfd91ba4..a32c5f3ab1 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -819,6 +819,8 @@ typedef struct CPUArchState {\n void *gicv3state;\n /* Similarly, for a GICv5Common */\n void *gicv5state;\n+ /* For GICv5, this CPU's IAFFID */\n+ uint64_t gicv5_iaffid;\n #else /* CONFIG_USER_ONLY */\n /* For usermode syscall translation. */\n bool eabi;\ndiff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 8cf09791c1..005e2fa8d2 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -226,6 +226,17 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.icc_icsr_el1),\n .resetvalue = 0,\n },\n+ { .name = \"ICC_IAFFIDR_EL1\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 5,\n+ .access = PL1_R, .type = ARM_CP_NO_RAW,\n+ /* ICC_IAFFIDR_EL1 holds the IAFFID only, in its low bits */\n+ .fieldoffset = offsetof(CPUARMState, gicv5_iaffid),\n+ /*\n+ * The field is a constant value set in gicv5_set_gicv5state(),\n+ * so don't allow it to be overwritten by reset.\n+ */\n+ .resetfn = arm_cp_reset_ignore,\n+ },\n };\n \n void define_gicv5_cpuif_regs(ARMCPU *cpu)\n", "prefixes": [ "v2", "34/65" ] }