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GET /api/patches/2216927/?format=api
{ "id": 2216927, "url": "http://patchwork.ozlabs.org/api/patches/2216927/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-46-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-46-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:40", "name": "[v2,45/65] target/arm: GICv5 cpuif: Implement ICC_PCR_EL1", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bffd1826c94955aa43e15daf534d3648e42f6aac", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-46-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216927/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216927/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=HqKr8Rpy;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyxn3T9hz1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:25:49 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65CN-0007D0-GL; Fri, 27 Mar 2026 07:17:57 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CH-00075S-2q\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:49 -0400", "from mail-wm1-x330.google.com ([2a00:1450:4864:20::330])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CE-0008Mi-It\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:48 -0400", "by mail-wm1-x330.google.com with SMTP id\n 5b1f17b1804b1-48558d6ef83so18690575e9.3\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:46 -0700 (PDT)", "from lanath.. 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These hold the physical priority\nmask for each interrupt domain -- an HPPI is only sufficiently high\npriority to preempt if it is higher priority than this mask value.\nHere we just implement the access to this data.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/cpu.h | 1 +\n target/arm/tcg/gicv5-cpuif.c | 31 +++++++++++++++++++++++++++++++\n 2 files changed, 32 insertions(+)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 1263841a1d..651fccd59b 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -606,6 +606,7 @@ typedef struct CPUArchState {\n uint64_t icc_icsr_el1;\n uint64_t icc_apr[NUM_GICV5_DOMAINS];\n uint64_t icc_cr0[NUM_GICV5_DOMAINS];\n+ uint64_t icc_pcr[NUM_GICV5_DOMAINS];\n /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register */\n uint64_t ppi_active[GICV5_NUM_PPIS / 64];\n uint64_t ppi_hm[GICV5_NUM_PPIS / 64];\ndiff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 50aa81d74f..b44b0d5398 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -49,6 +49,8 @@ FIELD(ICC_CR0, LINK_IDLE, 2, 1)\n FIELD(ICC_CR0, IPPT, 32, 6)\n FIELD(ICC_CR0, PID, 38, 1)\n \n+FIELD(ICC_PCR, PRIORITY, 0, 5)\n+\n /*\n * We implement 24 bits of interrupt ID, the mandated 5 bits of priority,\n * and no legacy GICv3.3 vcpu interface (yet)\n@@ -383,6 +385,28 @@ static void gic_icc_cr0_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri)\n }\n }\n \n+static uint64_t gic_icc_pcr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)\n+{\n+ GICv5Domain domain = gicv5_logical_domain(env);\n+ return env->gicv5_cpuif.icc_pcr[domain];\n+}\n+\n+static void gic_icc_pcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ GICv5Domain domain = gicv5_logical_domain(env);\n+\n+ value &= R_ICC_PCR_PRIORITY_MASK;\n+ env->gicv5_cpuif.icc_pcr[domain] = value;\n+}\n+\n+static void gic_icc_pcr_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri)\n+{\n+ for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.icc_pcr); i++) {\n+ env->gicv5_cpuif.icc_pcr[i] = 0;\n+ }\n+}\n+\n static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n /*\n * Barrier: wait until the effects of a cpuif system register\n@@ -548,6 +572,13 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n .writefn = gic_icc_cr0_el1_write,\n .resetfn = gic_icc_cr0_el1_reset,\n },\n+ { .name = \"ICC_PCR_EL1\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 2,\n+ .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .readfn = gic_icc_pcr_el1_read,\n+ .writefn = gic_icc_pcr_el1_write,\n+ .resetfn = gic_icc_pcr_el1_reset,\n+ },\n { .name = \"ICC_HAPR_EL1\", .state = ARM_CP_STATE_AA64,\n .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 3,\n .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n", "prefixes": [ "v2", "45/65" ] }