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GET /api/patches/2216923/?format=api
{ "id": 2216923, "url": "http://patchwork.ozlabs.org/api/patches/2216923/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-53-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-53-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:47", "name": "[v2,52/65] target/arm: GICv5 cpuif: Signal IRQ or FIQ", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "32051bb32134c35b11d360ceaf0856762f9d02b4", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-53-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216923/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216923/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=NVgWrZ40;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyww5pYHz1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:25:04 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65DS-0000NU-Pf; Fri, 27 Mar 2026 07:19:04 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CN-0007EK-JR\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:57 -0400", "from mail-wm1-x329.google.com ([2a00:1450:4864:20::329])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CL-0008Ro-Eq\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:55 -0400", "by mail-wm1-x329.google.com with SMTP id\n 5b1f17b1804b1-486fc4725f0so17975015e9.1\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:52 -0700 (PDT)", "from lanath.. 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Implement this logic.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/tcg/gicv5-cpuif.c | 87 ++++++++++++++++++++++++++++++++++--\n target/arm/tcg/trace-events | 1 +\n 2 files changed, 85 insertions(+), 3 deletions(-)", "diff": "diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 94590bd765..7caf2102a9 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -170,6 +170,84 @@ static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv5Domain domain)\n return best;\n }\n \n+static void cpu_interrupt_update(CPUARMState *env, int irqtype, bool new_state)\n+{\n+ CPUState *cs = env_cpu(env);\n+\n+ /*\n+ * OPT: calling cpu_interrupt() and cpu_reset_interrupt() has the\n+ * correct behaviour, but is not optimal for the case where we're\n+ * setting the interrupt line to the same level it already has.\n+ *\n+ * Clearing an already clear interrupt is free (it's just doing an\n+ * atomic AND operation). Signalling an already set interrupt is a\n+ * bit less ideal (it might unnecessarily kick the CPU).\n+ *\n+ * We could potentially use cpu_test_interrupt(), like\n+ * arm_cpu_update_{virq,vfiq,vinmi,vserr}, since we always hold\n+ * the BQL here; or perhaps there is an abstraction we could\n+ * provide in the core code that all these places could call.\n+ *\n+ * For now, this is simple and definitely correct.\n+ */\n+ if (new_state) {\n+ cpu_interrupt(cs, irqtype);\n+ } else {\n+ cpu_reset_interrupt(cs, irqtype);\n+ }\n+}\n+\n+static void gicv5_update_irq_fiq(CPUARMState *env)\n+{\n+ /*\n+ * Update whether we are signalling IRQ or FIQ based on the\n+ * current state of the CPU interface (and in particular on the\n+ * HPPI information from the IRS and for the PPIs for each\n+ * interrupt domain);\n+ *\n+ * The logic here for IRQ and FIQ is defined by rules R_QLGBG and\n+ * R_ZGHMN; whether to signal with superpriority is defined by\n+ * rule R_CSBDX.\n+ *\n+ * For the moment, we do not consider preemptive interrupts,\n+ * because these only occur when there is a HPPI of sufficient\n+ * priority for another interrupt domain, and we only support EL1\n+ * and the NonSecure interrupt domain currently.\n+ *\n+ * NB: when we handle more than just EL1 we will need to arrange\n+ * to call this function to re-evaluate the IRQ and FIQ state when\n+ * we change EL.\n+ */\n+ GICv5PendingIrq current_hppi;\n+ bool irq, fiq, superpriority;\n+\n+ /*\n+ * We will never signal FIQ because FIQ is for preemptive\n+ * interrupts or for EL3 HPPIs.\n+ */\n+ fiq = false;\n+\n+ /*\n+ * We signal IRQ when we are not signalling FIQ and there is a\n+ * HPPI of sufficient priority for the current domain. It has\n+ * Superpriority if its priority is 0 (in which case it is\n+ * CPU_INTERRUPT_NMI rather than CPU_INTERRUPT_HARD).\n+ */\n+ current_hppi = gic_hppi(env, gicv5_current_phys_domain(env));\n+ superpriority = current_hppi.prio == 0;\n+ irq = current_hppi.prio != PRIO_IDLE && !superpriority;\n+\n+ /*\n+ * Unlike a GICv3 or GICv2, there is no external IRQ or FIQ line\n+ * to the CPU. Instead we directly signal the interrupt via\n+ * cpu_interrupt()/cpu_reset_interrupt().\n+ */\n+ trace_gicv5_update_irq_fiq(irq, fiq, superpriority);\n+ cpu_interrupt_update(env, CPU_INTERRUPT_HARD, irq);\n+ cpu_interrupt_update(env, CPU_INTERRUPT_FIQ, fiq);\n+ cpu_interrupt_update(env, CPU_INTERRUPT_NMI, superpriority);\n+}\n+\n static void gic_recalc_ppi_hppi(CPUARMState *env)\n {\n /*\n@@ -219,15 +297,16 @@ static void gic_recalc_ppi_hppi(CPUARMState *env)\n env->gicv5_cpuif.ppi_hppi[i].intid,\n env->gicv5_cpuif.ppi_hppi[i].prio);\n }\n+ gicv5_update_irq_fiq(env);\n }\n \n void gicv5_forward_interrupt(ARMCPU *cpu, GICv5Domain domain)\n {\n /*\n- * For now, we do nothing. Later we will recalculate the overall\n- * HPPI by combining the IRS HPPI with the PPI HPPI, and possibly\n- * signal IRQ/FIQ.\n+ * IRS HPPI has changed: recalculate the IRQ/FIQ levels by\n+ * combining the IRS HPPI with the PPI HPPI.\n */\n+ gicv5_update_irq_fiq(&cpu->env);\n }\n \n static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri,\n@@ -430,6 +509,7 @@ static void gic_icc_cr0_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,\n value |= R_ICC_CR0_LINK_MASK | R_ICC_CR0_LINK_IDLE_MASK;\n \n env->gicv5_cpuif.icc_cr0[domain] = value;\n+ gicv5_update_irq_fiq(env);\n }\n \n static void gic_icc_cr0_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri)\n@@ -571,6 +651,7 @@ static void gic_cdeoi_write(CPUARMState *env, const ARMCPRegInfo *ri,\n \n /* clear lowest bit, doing nothing if already zero */\n *apr &= *apr - 1;\n+ gicv5_update_irq_fiq(env);\n }\n \n static void gic_cddi_write(CPUARMState *env, const ARMCPRegInfo *ri,\ndiff --git a/target/arm/tcg/trace-events b/target/arm/tcg/trace-events\nindex c60ce6834e..2bfa8fc552 100644\n--- a/target/arm/tcg/trace-events\n+++ b/target/arm/tcg/trace-events\n@@ -7,3 +7,4 @@ gicv5_gicr_cdia_fail(int domain, const char *reason) \"domain %d CDIA attempt fai\n gicv5_gicr_cdia(int domain, uint32_t id) \"domain %d CDIA acknowledge of interrupt 0x%x\"\n gicv5_cdeoi(int domain) \"domain %d CDEOI performing priority drop\"\n gicv5_cddi(int domain, uint32_t id) \"domain %d CDDI deactivating interrupt ID 0x%x\"\n+gicv5_update_irq_fiq(bool irq, bool fiq, bool nmi) \"now IRQ %d FIQ %d NMI %d\"\n", "prefixes": [ "v2", "52/65" ] }