Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2216891/?format=api
{ "id": 2216891, "url": "http://patchwork.ozlabs.org/api/patches/2216891/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-11-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-11-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:05", "name": "[v2,10/65] hw/intc/arm_gicv5: Implement IRS ID regs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "abc4907bfdb94b58d256f6b5c267b746df0b46ea", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-11-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216891/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216891/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=wZI2/gjV;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyrC4lBhz1yFr\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:20:59 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Bp-0006Tc-7q; Fri, 27 Mar 2026 07:17:21 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bk-0006Q8-OS\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:17 -0400", "from mail-wr1-x434.google.com ([2a00:1450:4864:20::434])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bh-0007oM-HG\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:16 -0400", "by mail-wr1-x434.google.com with SMTP id\n ffacd0b85a97d-439d8df7620so1408911f8f.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:13 -0700 (PDT)", "from lanath.. (wildly.archaic.org.uk. [81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.10\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 27 Mar 2026 04:17:11 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1774610232; x=1775215032; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=bXiijkgjBmWXs5fWCEwDdMcGLXqq1ZdmOeeZ74VWNOI=;\n b=wZI2/gjVtjPPmzMbGx5pppjSbNh4ocqvcbeGD1s6tfnSZ2ZPURakiSORoErorDZCZJ\n 4yVwANy7hJ/wWblRKyy/XHmm0YEIGUfzTvlDfD89fsDPWIDkhlXVn4L8jSXqusZr3MQG\n 44xv8GQBS2mvysVtuNUI14lfSPdoYGm8EwL0bczjiaBGKCmd4KAw/kmKBmz4jBNZ6uFS\n 5Z1YhUfxR/4OCun1rWfNOQZqaN9+n5CJ3I75HjdxrPqxH34TkFpKqFpvjSR8hlcKKsxv\n hLPkxvcGUZANhmVvVVz0isT4jDOfdsx1xUyUqOXbfE70whw8IUilWSvJhfRX+3kNF/cY\n euJw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774610232; x=1775215032;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=bXiijkgjBmWXs5fWCEwDdMcGLXqq1ZdmOeeZ74VWNOI=;\n b=nE1UOYPJeP4ZbHt4LLXkcVRpv/gdHEajrcAJtXHjgXlt9UZQS9hsYZ+tnMRMw+ALxP\n 1zTi8HYNBXGJ7mYazl20gS088xJpSnba4vUUeQ1ZX4rG0itB3zBKsY7Od3qOD28rz3G3\n gTYKbsP0p1d5FCZlGDaYs969Y5kHSyharr9EPowx9CnzNKxF8dRLdWZebYdqZhh3b9NH\n o8C1i60rssIUnJGBA10iDEbfJW7OYvt1YLke/ewuVUx2cCz6RbDbo/WjmdZ2dax41NvG\n 2uKZdXLC40jDAosfbISf1vhZuhMgNDgSeRAH62V71G4UcqvTifkk27xuIgRUZvtyMJhE\n n2eQ==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCXK6WKE8MDJcdWZXmjNZX7ugMgezSJOTm5U3lEK0CZC2X9gCCJe40mLitbNZEb6/bP8C5cRMrfuli7F@nongnu.org", "X-Gm-Message-State": "AOJu0YyG1GPnUzO7IGZEWXrLLL6O7o1c+cPoneJM1FLjswXIqwEf3fSY\n HX92qjwRqx1nmAXZLo3NqT4XjgdjCL8n8hXfBLXNUQLajh7JPHH+CPV8qQD8Iu5avab2TsEMOiM\n FaNR+3UA=", "X-Gm-Gg": "ATEYQzwLN/b4UeEOCB8fhgOgEcoGW0cUIXsZgXfdQy8D5c/2vJGb45wqQlZR5iTem8l\n +OIbbnM9rTBaFjQgZvlxrmwG4k/CSsaCHR2/EBsiM2+xu7UvNrlSQ7cbMzdlhSrbstuwuvBIqnM\n nmthOrr5CDMDGDdlwzCGzxNIaJw+H3YvS3wmKVOiD3K3HZshYrD+7SpPols8quc1PO3uyVi294G\n B+dZsK6+V5TmrkwQbNFGGa4+wy2MrPbONijQYX1Ds/7g5JeBgz1JxNpeL8G0yzw7WPDcHshjsFE\n HD9q1W/u4Gi6BZhnpOfXyOFD3e+cN1u20DHFVN+jfYGCd+MTToiD15Kaltv1AOa9EvwbTloP0bK\n 2wqmKxPycqvSh0ihRYwOeIQvxaiH63UCRYE6fi93V7oZqZbfPSrOn9qPyFjTu3MjD3a0v3ALVBQ\n mm16jp6W/960tYxfzkjaR450hgcxnCAEVSHFIwZplHjBUvWn7J/P/iZBMvShZPdR0y69PBpY3sh\n c435Ri/iBGSKtohY19Od/HFiyrE4kE=", "X-Received": "by 2002:a05:6000:2313:b0:43b:905d:f89f with SMTP id\n ffacd0b85a97d-43b9ea66dccmr3277541f8f.39.1774610231739;\n Fri, 27 Mar 2026 04:17:11 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Jonathan Cameron <jonathan.cameron@huawei.com>", "Subject": "[PATCH v2 10/65] hw/intc/arm_gicv5: Implement IRS ID regs", "Date": "Fri, 27 Mar 2026 11:16:05 +0000", "Message-ID": "<20260327111700.795099-11-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327111700.795099-1-peter.maydell@linaro.org>", "References": "<20260327111700.795099-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::434;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Implement the IRS frame ID registers IRS_IDR[0-7], IRS_IIDR and\nIRS_AIDR. These are all 32-bit registers.\n\nWe make these fields in the GIC state struct rather than just\nhardcoding them in the register read function so that we can later\ncode \"do this only if X is implemented\" as a test on the ID register\nvalue.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/intc/arm_gicv5.c | 115 +++++++++++++++++++++++++++++\n include/hw/intc/arm_gicv5_common.h | 38 ++++++++++\n 2 files changed, 153 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex 4c1ec8f30a..250925f004 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -268,6 +268,65 @@ REG64(IRS_SWERR_SYNDROMER1, 0x3d0)\n static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,\n uint64_t *data, MemTxAttrs attrs)\n {\n+ GICv5Common *cs = ARM_GICV5_COMMON(s);\n+ uint32_t v = 0;\n+\n+ switch (offset) {\n+ case A_IRS_IDR0:\n+ v = cs->irs_idr0;\n+ /* INT_DOM reports the domain this register is for */\n+ v = FIELD_DP32(v, IRS_IDR0, INT_DOM, domain);\n+ if (domain != GICV5_ID_REALM) {\n+ /* MEC field RES0 except for the Realm domain */\n+ v &= ~R_IRS_IDR0_MEC_MASK;\n+ }\n+ if (domain == GICV5_ID_EL3) {\n+ /* VIRT is RES0 for EL3 domain */\n+ v &= ~R_IRS_IDR0_VIRT_MASK;\n+ /* ...which means VIRT_ONE_N is also RES0 */\n+ v &= ~R_IRS_IDR0_VIRT_ONE_N_MASK;\n+ }\n+ return true;\n+\n+ case A_IRS_IDR1:\n+ *data = cs->irs_idr1;\n+ return true;\n+\n+ case A_IRS_IDR2:\n+ *data = cs->irs_idr2;\n+ return true;\n+\n+ case A_IRS_IDR3:\n+ /* In EL3 IDR0.VIRT is 0 so this is RES0 */\n+ *data = domain == GICV5_ID_EL3 ? 0 : cs->irs_idr3;\n+ return true;\n+\n+ case A_IRS_IDR4:\n+ /* In EL3 IDR0.VIRT is 0 so this is RES0 */\n+ *data = domain == GICV5_ID_EL3 ? 0 : cs->irs_idr4;\n+ return true;\n+\n+ case A_IRS_IDR5:\n+ *data = cs->irs_idr5;\n+ return true;\n+\n+ case A_IRS_IDR6:\n+ *data = cs->irs_idr6;\n+ return true;\n+\n+ case A_IRS_IDR7:\n+ *data = cs->irs_idr7;\n+ return true;\n+\n+ case A_IRS_IIDR:\n+ *data = cs->irs_iidr;\n+ return true;\n+\n+ case A_IRS_AIDR:\n+ *data = cs->irs_aidr;\n+ return true;\n+ }\n+\n return false;\n }\n \n@@ -422,6 +481,60 @@ static void gicv5_reset_hold(Object *obj, ResetType type)\n }\n }\n \n+static void gicv5_set_idregs(GICv5Common *cs)\n+{\n+ /* Set the ID register value fields */\n+ uint32_t v;\n+\n+ /*\n+ * Fields in IDR0 for optional parts of the spec that we don't\n+ * implement are 0.\n+ */\n+ v = 0;\n+ /*\n+ * We can handle physical addresses of any size, so report support\n+ * for 56 bits of physical address space.\n+ */\n+ v = FIELD_DP32(v, IRS_IDR0, PA_RANGE, 7);\n+ v = FIELD_DP32(v, IRS_IDR0, IRSID, cs->irsid);\n+ cs->irs_idr0 = v;\n+\n+ v = 0;\n+ v = FIELD_DP32(v, IRS_IDR1, PE_CNT, cs->num_cpus);\n+ v = FIELD_DP32(v, IRS_IDR1, IAFFID_BITS, QEMU_GICV5_IAFFID_BITS - 1);\n+ v = FIELD_DP32(v, IRS_IDR1, PRI_BITS, QEMU_GICV5_PRI_BITS - 1);\n+ cs->irs_idr1 = v;\n+\n+ v = 0;\n+ /* We always support physical LPIs with 2-level ISTs of all sizes */\n+ v = FIELD_DP32(v, IRS_IDR2, ID_BITS, QEMU_GICV5_ID_BITS);\n+ v = FIELD_DP32(v, IRS_IDR2, LPI, 1);\n+ v = FIELD_DP32(v, IRS_IDR2, MIN_LPI_ID_BITS, QEMU_GICV5_MIN_LPI_ID_BITS);\n+ v = FIELD_DP32(v, IRS_IDR2, IST_LEVELS, 1);\n+ v = FIELD_DP32(v, IRS_IDR2, IST_L2SZ, 7);\n+ /* Our impl does not need IST metadata, so ISTMD and ISTMD_SZ are 0 */\n+ cs->irs_idr2 = v;\n+\n+ /* We don't implement virtualization yet, so these are zero */\n+ cs->irs_idr3 = 0;\n+ cs->irs_idr4 = 0;\n+\n+ /* These three have just one field each */\n+ cs->irs_idr5 = FIELD_DP32(0, IRS_IDR5, SPI_RANGE, cs->spi_range);\n+ cs->irs_idr6 = FIELD_DP32(0, IRS_IDR6, SPI_IRS_RANGE, cs->spi_irs_range);\n+ cs->irs_idr7 = FIELD_DP32(0, IRS_IDR7, SPI_BASE, cs->spi_base);\n+\n+ v = 0;\n+ v = FIELD_DP32(v, IRS_IIDR, IMPLEMENTER, QEMU_GICV5_IMPLEMENTER);\n+ v = FIELD_DP32(v, IRS_IIDR, REVISION, QEMU_GICV5_REVISION);\n+ v = FIELD_DP32(v, IRS_IIDR, VARIANT, QEMU_GICV5_VARIANT);\n+ v = FIELD_DP32(v, IRS_IIDR, PRODUCTID, QEMU_GICV5_PRODUCTID);\n+ cs->irs_iidr = v;\n+\n+ /* This is a GICv5.0 IRS, so all fields are zero */\n+ cs->irs_aidr = 0;\n+}\n+\n static void gicv5_realize(DeviceState *dev, Error **errp)\n {\n GICv5Common *cs = ARM_GICV5_COMMON(dev);\n@@ -448,6 +561,8 @@ static void gicv5_realize(DeviceState *dev, Error **errp)\n * NS domain.\n */\n cs->implemented_domains = (1 << GICV5_ID_NS);\n+\n+ gicv5_set_idregs(cs);\n gicv5_common_init_irqs_and_mmio(cs, gicv5_set_spi, config_frame_ops);\n }\n \ndiff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5_common.h\nindex 10276d652f..906870e49f 100644\n--- a/include/hw/intc/arm_gicv5_common.h\n+++ b/include/hw/intc/arm_gicv5_common.h\n@@ -65,6 +65,18 @@ struct GICv5Common {\n /* Bits here are set for each physical interrupt domain implemented */\n uint8_t implemented_domains;\n \n+ /* ID register values: set at realize, constant thereafter */\n+ uint32_t irs_idr0;\n+ uint32_t irs_idr1;\n+ uint32_t irs_idr2;\n+ uint32_t irs_idr3;\n+ uint32_t irs_idr4;\n+ uint32_t irs_idr5;\n+ uint32_t irs_idr6;\n+ uint32_t irs_idr7;\n+ uint32_t irs_iidr;\n+ uint32_t irs_aidr;\n+\n /* Properties */\n uint32_t num_cpus;\n ARMCPU **cpus;\n@@ -84,6 +96,32 @@ struct GICv5CommonClass {\n \n #define IRS_CONFIG_FRAME_SIZE 0x10000\n \n+/*\n+ * The architecture allows a GICv5 to implement less than the full\n+ * width for various ID fields. QEMU's implementation always supports\n+ * the full width of these fields. These constants define our\n+ * implementation's limits.\n+ */\n+\n+/* Number of INTID.ID bits we support */\n+#define QEMU_GICV5_ID_BITS 24\n+/* Min LPI_ID_BITS supported */\n+#define QEMU_GICV5_MIN_LPI_ID_BITS 14\n+/* IAFFID bits supported */\n+#define QEMU_GICV5_IAFFID_BITS 16\n+/* Number of priority bits supported in the IRS */\n+#define QEMU_GICV5_PRI_BITS 5\n+\n+/*\n+ * There are no TRMs currently published for hardware implementations\n+ * of GICv5 that we might identify ourselves as. Instead, we borrow\n+ * the Arm Implementer code and pick an arbitrary product ID (ASCII \"Q\")\n+ */\n+#define QEMU_GICV5_IMPLEMENTER 0x43b\n+#define QEMU_GICV5_PRODUCTID 0x51\n+#define QEMU_GICV5_REVISION 0\n+#define QEMU_GICV5_VARIANT 0\n+\n /**\n * gicv5_common_init_irqs_and_mmio: Create IRQs and MMIO regions for the GICv5\n * @s: GIC object\n", "prefixes": [ "v2", "10/65" ] }