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GET /api/patches/2216903/?format=api
{ "id": 2216903, "url": "http://patchwork.ozlabs.org/api/patches/2216903/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-55-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-55-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:49", "name": "[v2,54/65] target/arm: Add has_gcie property to enable FEAT_GCIE", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "15636a9cbb8783e745043da1f6829d4ed31af9f1", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-55-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216903/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216903/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=RFBJH/+D;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhytG0VQ0z1yFr\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:22:46 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Dk-0001AX-Gd; Fri, 27 Mar 2026 07:19:20 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CT-0007RY-Oy\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:02 -0400", "from mail-wr1-x430.google.com ([2a00:1450:4864:20::430])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CN-0008VI-Ag\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:59 -0400", "by mail-wr1-x430.google.com with SMTP id\n ffacd0b85a97d-43b5bded412so1432756f8f.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:54 -0700 (PDT)", "from lanath.. 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So\nthere are no GIC control system registers defined for AArch32. We\nforce AArch32 at ELs 1, 2 and 3 to disabled, to avoid a guest being\nable to get into an EL where interrupts are completely broken.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/cpu.c | 45 +++++++++++++++++++++++++++++++++++++++\n target/arm/cpu.h | 2 ++\n 3 files changed, 52 insertions(+)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex e391b394ba..c0ba56f244 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1072,6 +1072,11 @@ static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL2) >= 2;\n }\n \n+static inline bool isar_feature_aa64_aa32_el3(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL3) >= 2;\n+}\n+\n static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)\n {\n return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) != 0;\ndiff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex ceb303a55a..21c2953501 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -1197,6 +1197,9 @@ static const Property arm_cpu_has_el2_property =\n \n static const Property arm_cpu_has_el3_property =\n DEFINE_PROP_BOOL(\"has_el3\", ARMCPU, has_el3, true);\n+\n+static const Property arm_cpu_has_gcie_property =\n+ DEFINE_PROP_BOOL(\"has_gcie\", ARMCPU, has_gcie, false);\n #endif\n \n static const Property arm_cpu_cfgend_property =\n@@ -1425,6 +1428,11 @@ static void arm_cpu_post_init(Object *obj)\n object_property_add_uint64_ptr(obj, \"rvbar\",\n &cpu->rvbar_prop,\n OBJ_PROP_FLAG_READWRITE);\n+\n+ /* We only allow GICv5 on a 64-bit v8 CPU */\n+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {\n+ qdev_property_add_static(DEVICE(obj), &arm_cpu_has_gcie_property);\n+ }\n }\n \n if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {\n@@ -1699,6 +1707,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)\n current_accel_name());\n return;\n }\n+ if (cpu->has_gcie) {\n+ error_setg(errp,\n+ \"Cannot enable %s when guest CPU has GICv5 enabled\",\n+ current_accel_name());\n+ return;\n+ }\n }\n #endif\n \n@@ -2022,6 +2036,37 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)\n FIELD_DP32_IDREG(isar, ID_PFR1, VIRTUALIZATION, 0);\n }\n \n+ /* Report FEAT_GCIE in our ID registers if property was set */\n+ FIELD_DP64_IDREG(isar, ID_AA64PFR2, GCIE, cpu->has_gcie);\n+ if (cpu_isar_feature(aa64_gcie, cpu)) {\n+ if (!arm_feature(env, ARM_FEATURE_AARCH64)) {\n+ /*\n+ * We only create the have_gcie property for AArch64 CPUs,\n+ * but the user might have tried aarch64=off with has_gcie=on.\n+ */\n+ error_setg(errp, \"Cannot both enable has_gcie and disable aarch64\");\n+ return;\n+ }\n+\n+ /*\n+ * FEAT_GCIE implies Armv9, which implies no AArch32 above EL0.\n+ * Usually we don't strictly insist on this kind of feature\n+ * dependency, but in this case we enforce it, because the\n+ * GICv5 CPU interface has no AArch32 versions of its system\n+ * registers, so interrupts wouldn't work if we allowed AArch32\n+ * in EL1 or above. Downgrade \"AArch32 and AArch64\" to \"AArch64\".\n+ */\n+ if (cpu_isar_feature(aa64_aa32_el3, cpu)) {\n+ FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 1);\n+ }\n+ if (cpu_isar_feature(aa64_aa32_el2, cpu)) {\n+ FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 1);\n+ }\n+ if (cpu_isar_feature(aa64_aa32_el1, cpu)) {\n+ FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL1, 1);\n+ }\n+ }\n+\n if (cpu_isar_feature(aa64_mte, cpu)) {\n /*\n * The architectural range of GM blocksize is 2-6, however qemu\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 651fccd59b..a5f27dfe0f 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -1032,6 +1032,8 @@ struct ArchCPU {\n bool has_neon;\n /* CPU has M-profile DSP extension */\n bool has_dsp;\n+ /* CPU has FEAT_GCIE GICv5 CPU interface */\n+ bool has_gcie;\n \n /* CPU has memory protection unit */\n bool has_mpu;\n", "prefixes": [ "v2", "54/65" ] }