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GET /api/patches/2216930/?format=api
{ "id": 2216930, "url": "http://patchwork.ozlabs.org/api/patches/2216930/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-25-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-25-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:19", "name": "[v2,24/65] hw/intc/arm_gicv5: Make gicv5_set_* update SPI state", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "560a74fa7e104b1f88faccf7ff8c250c75916d2e", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-25-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216930/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216930/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=cFUR6h7y;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyy04Wyvz1yFx\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:26:00 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65C1-0006lF-Ke; Fri, 27 Mar 2026 07:17:33 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bw-0006eC-Kq\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:28 -0400", "from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bu-0007xa-MQ\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:28 -0400", "by mail-wr1-x42f.google.com with SMTP id\n ffacd0b85a97d-439b2965d4bso1506705f8f.2\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:26 -0700 (PDT)", "from lanath.. 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helo=mail-wr1-x42f.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The GIC CD* insns that update interrupt state also work for SPIs.\nInstead of ignoring the GICV5_SPI type in gicv5_set_priority() and\nfriends, update the state in our SPI state array.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/intc/arm_gicv5.c | 64 ++++++++++++++++++++++++++++++\n include/hw/intc/arm_gicv5_common.h | 40 +++++++++++++++++++\n 2 files changed, 104 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex d1eb96fce0..9ca1826253 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -490,6 +490,19 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id, uint8_t priority,\n put_l2_iste(cs, cfg, &h);\n break;\n }\n+ case GICV5_SPI:\n+ {\n+ GICv5SPIState *spi = gicv5_spi_state(cs, id, domain);\n+\n+ if (!spi) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_priority: tried to set \"\n+ \"priority of unreachable SPI %d\\n\", id);\n+ return;\n+ }\n+\n+ spi->priority = priority;\n+ break;\n+ }\n default:\n qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_priority: tried to set \"\n \"priority of bad interrupt type %d\\n\", type);\n@@ -524,6 +537,19 @@ void gicv5_set_enabled(GICv5Common *cs, uint32_t id, bool enabled,\n put_l2_iste(cs, cfg, &h);\n break;\n }\n+ case GICV5_SPI:\n+ {\n+ GICv5SPIState *spi = gicv5_spi_state(cs, id, domain);\n+\n+ if (!spi) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_enabled: tried to set \"\n+ \"enable state of unreachable SPI %d\\n\", id);\n+ return;\n+ }\n+\n+ spi->enabled = true;\n+ break;\n+ }\n default:\n qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_enabled: tried to set \"\n \"enable state of bad interrupt type %d\\n\", type);\n@@ -558,6 +584,19 @@ void gicv5_set_pending(GICv5Common *cs, uint32_t id, bool pending,\n put_l2_iste(cs, cfg, &h);\n break;\n }\n+ case GICV5_SPI:\n+ {\n+ GICv5SPIState *spi = gicv5_spi_state(cs, id, domain);\n+\n+ if (!spi) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_pending: tried to set \"\n+ \"pending state of unreachable SPI %d\\n\", id);\n+ return;\n+ }\n+\n+ spi->pending = true;\n+ break;\n+ }\n default:\n qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_pending: tried to set \"\n \"pending state of bad interrupt type %d\\n\", type);\n@@ -593,6 +632,18 @@ void gicv5_set_handling(GICv5Common *cs, uint32_t id,\n put_l2_iste(cs, cfg, &h);\n break;\n }\n+ case GICV5_SPI:\n+ {\n+ GICv5SPIState *spi = gicv5_spi_state(cs, id, domain);\n+\n+ if (!spi) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_handling: tried to set \"\n+ \"priority of unreachable SPI %d\\n\", id);\n+ }\n+\n+ spi->hm = handling;\n+ break;\n+ }\n default:\n qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_handling: tried to set \"\n \"handling mode of bad interrupt type %d\\n\", type);\n@@ -642,6 +693,19 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, uint32_t iaffid,\n put_l2_iste(cs, cfg, &h);\n break;\n }\n+ case GICV5_SPI:\n+ {\n+ GICv5SPIState *spi = gicv5_spi_state(cs, id, domain);\n+\n+ if (!spi) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_target: tried to set \"\n+ \"target of unreachable SPI %d\\n\", id);\n+ return;\n+ }\n+\n+ spi->iaffid = iaffid;\n+ break;\n+ }\n default:\n qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_set_target: tried to set \"\n \"target of bad interrupt type %d\\n\", type);\ndiff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5_common.h\nindex d3f4999321..a81c941765 100644\n--- a/include/hw/intc/arm_gicv5_common.h\n+++ b/include/hw/intc/arm_gicv5_common.h\n@@ -189,4 +189,44 @@ static inline bool gicv5_domain_implemented(GICv5Common *cs, GICv5Domain domain)\n */\n const char *gicv5_class_name(void);\n \n+/**\n+ * gicv5_raw_spi_state\n+ * @cs: GIC object\n+ * @id: INTID of SPI to look up\n+ *\n+ * Return pointer to the GICv5SPIState for this SPI, or NULL if the\n+ * interrupt ID is out of range. This does not do a check that the SPI\n+ * is assigned to the right domain: generally you should call it via\n+ * some other wrapper that performs an appropriate further check.\n+ */\n+static inline GICv5SPIState *gicv5_raw_spi_state(GICv5Common *cs, uint32_t id)\n+{\n+ if (id < cs->spi_base || id >= cs->spi_base + cs->spi_irs_range) {\n+ return NULL;\n+ }\n+\n+ return cs->spi + (id - cs->spi_base);\n+}\n+\n+/**\n+ * gicv5_spi_state:\n+ * @cs: GIC object\n+ * @id: INTID of SPI to look up\n+ * @domain: domain to check\n+ *\n+ * Return pointer to the GICv5SPIState for this SPI, or NULL if the\n+ * interrupt is unreachable (which can be because the INTID is out of\n+ * range, or because the SPI is configured for a different domain).\n+ */\n+static inline GICv5SPIState *gicv5_spi_state(GICv5Common *cs, uint32_t id,\n+ GICv5Domain domain)\n+{\n+ GICv5SPIState *spi = gicv5_raw_spi_state(cs, id);\n+\n+ if (!spi || spi->domain != domain) {\n+ return NULL;\n+ }\n+ return spi;\n+}\n+\n #endif\n", "prefixes": [ "v2", "24/65" ] }