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GET /api/patches/2216916/?format=api
{ "id": 2216916, "url": "http://patchwork.ozlabs.org/api/patches/2216916/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-63-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-63-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:57", "name": "[v2,62/65] hw/arm/virt: Handle GICv5 in interrupt bindings for PPIs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "564893a7bb313e1b394388a155118398e1de6340", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-63-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216916/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216916/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Gzb8LvQs;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyvW1LkXz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:23:51 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Du-0002HY-Mr; Fri, 27 Mar 2026 07:19:30 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CY-0007aI-R6\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:07 -0400", "from mail-wr1-x436.google.com ([2a00:1450:4864:20::436])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CV-0000HU-9Q\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:06 -0400", "by mail-wr1-x436.google.com with SMTP id\n ffacd0b85a97d-43b3d9d0695so1384743f8f.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:18:02 -0700 (PDT)", "from lanath.. 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(The third field defining the level/edge trigger mode has\nthe same values for GICv5 as it did for the older GICs.)\n\nIn the places in the virt board where we wire up PPIs (the timer and\nthe PMU), handle the GICv5:\n\n * use the architectural constant GICV5_PPI for the type\n * use the architected GICv5 PPI numbers for the interrupt sources\n (which differ from the old ones and don't need to be adjusted via\n INTID_TO_PPI())\n * leave the irqflags as-is\n\nAdd some commentary in our include/hw/arm/fdt.h file about what the\nthe constants defined there are valid for.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/arm/virt.c | 23 +++++++++++++++++++----\n include/hw/arm/fdt.h | 10 ++++++++++\n 2 files changed, 29 insertions(+), 4 deletions(-)", "diff": "diff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex 7a34af766a..bc49cf244f 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -420,7 +420,15 @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)\n \"arm,armv7-timer\");\n }\n qemu_fdt_setprop(ms->fdt, \"/timer\", \"always-on\", NULL, 0);\n- if (vms->ns_el2_virt_timer_irq) {\n+ if (vms->gic_version == VIRT_GIC_VERSION_5) {\n+ /* The GICv5 architects the PPI numbers differently */\n+ qemu_fdt_setprop_cells(ms->fdt, \"/timer\", \"interrupts\",\n+ GICV5_PPI, GICV5_PPI_CNTPS, irqflags,\n+ GICV5_PPI, GICV5_PPI_CNTP, irqflags,\n+ GICV5_PPI, GICV5_PPI_CNTV, irqflags,\n+ GICV5_PPI, GICV5_PPI_CNTHP, irqflags,\n+ GICV5_PPI, GICV5_PPI_CNTHV, irqflags);\n+ } else if (vms->ns_el2_virt_timer_irq) {\n qemu_fdt_setprop_cells(ms->fdt, \"/timer\", \"interrupts\",\n GIC_FDT_IRQ_TYPE_PPI,\n INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,\n@@ -699,11 +707,18 @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)\n qemu_fdt_add_subnode(ms->fdt, \"/pmu\");\n if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {\n const char compat[] = \"arm,armv8-pmuv3\";\n+\n qemu_fdt_setprop(ms->fdt, \"/pmu\", \"compatible\",\n compat, sizeof(compat));\n- qemu_fdt_setprop_cells(ms->fdt, \"/pmu\", \"interrupts\",\n- GIC_FDT_IRQ_TYPE_PPI,\n- INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags);\n+ if (vms->gic_version == VIRT_GIC_VERSION_5) {\n+ qemu_fdt_setprop_cells(ms->fdt, \"/pmu\", \"interrupts\",\n+ GICV5_PPI, GICV5_PPI_PMUIRQ, irqflags);\n+ } else {\n+ qemu_fdt_setprop_cells(ms->fdt, \"/pmu\", \"interrupts\",\n+ GIC_FDT_IRQ_TYPE_PPI,\n+ INTID_TO_PPI(VIRTUAL_PMU_IRQ),\n+ irqflags);\n+ }\n }\n }\n \ndiff --git a/include/hw/arm/fdt.h b/include/hw/arm/fdt.h\nindex c3d5015013..995652c27a 100644\n--- a/include/hw/arm/fdt.h\n+++ b/include/hw/arm/fdt.h\n@@ -20,9 +20,19 @@\n #ifndef QEMU_ARM_FDT_H\n #define QEMU_ARM_FDT_H\n \n+/*\n+ * These are for GICv2/v3/v4 only; GICv5 encodes the interrupt type in\n+ * the DTB \"interrupts\" properties differently, using constants that\n+ * match the architectural INTID.Type. In QEMU those are available as\n+ * the GICV5_PPI and GICV5_SPI enum values in arm_gicv5_types.h.\n+ */\n #define GIC_FDT_IRQ_TYPE_SPI 0\n #define GIC_FDT_IRQ_TYPE_PPI 1\n \n+/*\n+ * The trigger type/level field in the DTB \"interrupts\" property has\n+ * the same encoding for GICv2/v3/v4 and v5.\n+ */\n #define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1\n #define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2\n #define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4\n", "prefixes": [ "v2", "62/65" ] }