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GET /api/patches/2216896/?format=api
{ "id": 2216896, "url": "http://patchwork.ozlabs.org/api/patches/2216896/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-30-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-30-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:24", "name": "[v2,29/65] hw/intc/arm_gicv5: Implement IRS_CR0 and IRS_CR1", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "03ef6969f3877aeb2f8df5fd38ad92ac6819dbf5", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-30-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216896/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216896/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=QfqkyLE8;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhys938T7z1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:21:49 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65C5-0006qM-Hi; Fri, 27 Mar 2026 07:17:37 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C2-0006m9-86\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:34 -0400", "from mail-wr1-x433.google.com ([2a00:1450:4864:20::433])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bz-00081S-G9\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:33 -0400", "by mail-wr1-x433.google.com with SMTP id\n ffacd0b85a97d-439b9cf8cb5so1919201f8f.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:30 -0700 (PDT)", "from lanath.. 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helo=mail-wr1-x433.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The IRS_CR0 register has the main enable bit for the IRS, and an IDLE\nbit to tell the guest when an enable/disable transition has\ncompleted.\n\nThe IRS_CR1 register has cacheability, shareability and cache hint\ninformation to use for IRS memory accesses; since QEMU doesn't care\nabout this we can make it simply reads-as-written.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5.c | 13 +++++++++++++\n hw/intc/arm_gicv5_common.c | 2 ++\n include/hw/intc/arm_gicv5_common.h | 2 ++\n 3 files changed, 17 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex bc887233f5..3f397d9115 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -1080,6 +1080,13 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,\n }\n *data = v;\n return true;\n+ case A_IRS_CR0:\n+ /* Enabling is instantaneous for us so IDLE is always 1 */\n+ *data = cs->irs_cr0[domain] | R_IRS_CR0_IDLE_MASK;\n+ return true;\n+ case A_IRS_CR1:\n+ *data = cs->irs_cr1[domain];\n+ return true;\n }\n \n return false;\n@@ -1159,6 +1166,12 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset,\n trace_gicv5_spi_state(id, spi->level, spi->pending, spi->active);\n return true;\n }\n+ case A_IRS_CR0:\n+ cs->irs_cr0[domain] = data & R_IRS_CR0_IRSEN_MASK;\n+ return true;\n+ case A_IRS_CR1:\n+ cs->irs_cr1[domain] = data;\n+ return true;\n }\n \n return false;\ndiff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c\nindex 0813f0ac66..b1c8ec4521 100644\n--- a/hw/intc/arm_gicv5_common.c\n+++ b/hw/intc/arm_gicv5_common.c\n@@ -66,6 +66,8 @@ static void gicv5_common_reset_hold(Object *obj, ResetType type)\n \n memset(cs->irs_ist_baser, 0, sizeof(cs->irs_ist_baser));\n memset(cs->irs_ist_cfgr, 0, sizeof(cs->irs_ist_cfgr));\n+ memset(cs->irs_cr0, 0, sizeof(cs->irs_cr0));\n+ memset(cs->irs_cr1, 0, sizeof(cs->irs_cr1));\n \n if (cs->spi) {\n GICv5Domain mp_domain;\ndiff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5_common.h\nindex 61d017bf38..ac0532abe8 100644\n--- a/include/hw/intc/arm_gicv5_common.h\n+++ b/include/hw/intc/arm_gicv5_common.h\n@@ -84,6 +84,8 @@ struct GICv5Common {\n uint64_t irs_ist_baser[NUM_GICV5_DOMAINS];\n uint32_t irs_ist_cfgr[NUM_GICV5_DOMAINS];\n uint32_t irs_spi_selr[NUM_GICV5_DOMAINS];\n+ uint32_t irs_cr0[NUM_GICV5_DOMAINS];\n+ uint32_t irs_cr1[NUM_GICV5_DOMAINS];\n \n /*\n * Pointer to an array of state information for the SPIs. Array\n", "prefixes": [ "v2", "29/65" ] }