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GET /api/patches/2216902/?format=api
{ "id": 2216902, "url": "http://patchwork.ozlabs.org/api/patches/2216902/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-21-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-21-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:15", "name": "[v2,20/65] hw/intc/arm_gicv5: Implement IRS_MAP_L2_ISTR", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3f246316eee6c4cc418dec3bf29b4752b63acda4", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-21-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216902/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216902/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=FzXQNF5U;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhytF5Y9Rz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:22:45 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65C0-0006io-C2; Fri, 27 Mar 2026 07:17:32 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bs-0006Xt-CV\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:24 -0400", "from mail-wr1-x434.google.com ([2a00:1450:4864:20::434])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bq-0007vw-Eq\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:24 -0400", "by mail-wr1-x434.google.com with SMTP id\n ffacd0b85a97d-439b94a19fdso1876603f8f.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:21 -0700 (PDT)", "from lanath.. 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[81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.19\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 27 Mar 2026 04:17:20 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1774610241; x=1775215041; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=iFlZReDv+qQIw0DAeaun7wzY8NaJlNVkqk/yf85M5x8=;\n b=FzXQNF5U3EXkaEvMJ30UM51QB5TtiGoN7cTXZyGpM7C43HHKsJDCs4/nCrUlZjjA8r\n PkUFktMjuEGcnviwHNq2DvdSi74x0L/JOsmmz0kyS+b+t8oIwoGa+H4I6lrRbSmSItWX\n 2Xgnk5mz7+6S+VFZX2AjyMzAcw1foAP5V7pCqqM9DRz4la4bL/HeMxxgZA5d/+vc4btO\n mzylHFFJTBOfydFOHBQeDWEPUV1MeBg8sPLRVotoZYuvQgSFJTsmLfep1WFlIDeXFbYJ\n nIqrCNyL6r7J/TIIQjtVbPgHIduJPY3uMJaG/B1yy37yPBOmyuR8pTnOAEhavQz7hdCD\n /ZdQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774610241; x=1775215041;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=iFlZReDv+qQIw0DAeaun7wzY8NaJlNVkqk/yf85M5x8=;\n b=G7wdtU+dcCr1HTixW5yO5Zgm0F5Yhlc8U/8ctUApwkt2KQdpHcTE2BG9jo6SIYKREo\n ICJ1+tkWkZHCwINXWxiN0gEW1ksNn8kIaUmlTuTmL7KGcNrsMLwy2AV32Vj+ewcZOz/6\n qeFqENuBUoJVVL9RuCPynStyMmM3sduJPiNWkp01JI3DJROTqQuO4U94HDbeuboEbNk/\n u6eBBzOZ1OZyLfYBRMmNoLviU6AGyAfZg7jTzP2OJVBfGk1qRhhgsVKX5NBjiFtr8DAH\n SM7n2ZC6NWQj1fBiVxzwDBC12uBVihVaA0iaVJStMbk5ESaM3+pjREKRi4wjjEWYYu3D\n voYw==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCWg8L1Nj1ZxcaW6lqabVnLMN7LHMImIY10uoSy7e3xkezgdQqOKjCKA9CBwWzZEGB0wr132CGuVicBu@nongnu.org", "X-Gm-Message-State": "AOJu0YwEC6ZhIkeJluQJfgshJPUIFCG6Urq2oq4v2UhH+JD81geFxFbw\n 3TFhZUOQvHRX/ZK2bzrLRWdSMyc64lTsq8JNR9nvTYzaPyvnBIriyz7+tVml8EQMom4=", "X-Gm-Gg": "ATEYQzx3Yt+mcsxwfFe9y9X5vWB8AGKvmijCq13CZ5NAQkUol977yaESGdMhEivic/2\n EduiwrACu7gSAv+c2OCa/wsHPdGyEGL4/LquXOZXn37V8WSJJ/+WUBxhOGBCgoCKGzDD77wgVGa\n I/Tvyi2e+/nE3o89z90LaJ+y4VZz9AejkmKEHjakV76Hrljn1zRnp5CnnwstuOyx0OvANowqy/l\n ITamfGX2gb5OLaYjdWdaT8NmwLiFqnfc80c4sn+UMnGd43G2NXfJUlGV9yTFR0Q1GGYpf3vyURt\n 4afMeyaImhYESweFRw0uCtP0pcE2wQzBL9jt1I06H5QDSHWASvPEm2c0Hbxqp0dqMrQu3aWa+Vg\n N+wavGXiCK7hhfLug0pX34klqhm0NJEr12lmsrXS6SPPEbab4cHJS9Ac4stm7Djm6eKTLrTxNW9\n 4kAmLrVMh3sYvtDirGnpnOo8XTWsD1rEEb32jHhqIRcHeC0h3xeTcYI2eu+WrpGQQx8H+tSUQFh\n WQqIG+JpYK1jH2z4FmdAAukpCoXdmA+jo96DNsVEg==", "X-Received": "by 2002:a05:6000:2892:b0:43b:47bc:c147 with SMTP id\n ffacd0b85a97d-43b9ea66f1fmr3345875f8f.45.1774610240765;\n Fri, 27 Mar 2026 04:17:20 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Jonathan Cameron <jonathan.cameron@huawei.com>", "Subject": "[PATCH v2 20/65] hw/intc/arm_gicv5: Implement IRS_MAP_L2_ISTR", "Date": "Fri, 27 Mar 2026 11:16:15 +0000", "Message-ID": "<20260327111700.795099-21-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327111700.795099-1-peter.maydell@linaro.org>", "References": "<20260327111700.795099-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::434;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The IRS register IRS_MAP_L2_ISTR is used by software to tell the IRS\nthat it has updated the address in an L1 IST entry to point to an\nL2 IST. The sequence of events here is:\n * software writes to L1_ISTE.L2_ADDR for some L1 ISTE which is\n not valid (i.e. where L1_ISTE.VALID is 0); it leaves VALID at 0\n * software writes to IRS_MAP_L2_ISTR with some INTID that is inside\n the range for this L1 ISTE\n * the IRS sets IRS_IST_STATUSR.IDLE to 0\n * the IRS takes note of this information\n * the IRS writes to the L1_ISTE to set VALID=1\n * the IRS sets IRS_IST_STATUSR.IDLE to 1 to indicate that the\n update is complete\n\nFor QEMU, we're strictly synchronous, so (as with IRS_IST_BASER\nupdates) we don't need to model the IDLE transitions and can have\nIRS_IST_STATUSR always return IDLE=1. We also don't currently cache\nanything for ISTE lookups, so we don't need to invalidate or update\nanything when software makes the L2 valid.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5.c | 40 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 40 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex 3588f3323f..7d654a91e6 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -497,6 +497,43 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id, uint8_t priority,\n }\n }\n \n+static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t value)\n+{\n+ GICv5Common *cs = ARM_GICV5_COMMON(s);\n+ GICv5ISTConfig *cfg = &s->phys_lpi_config[domain];\n+ uint32_t intid = FIELD_EX32(value, IRS_MAP_L2_ISTR, ID);\n+ hwaddr l1_addr;\n+ uint64_t l1_iste;\n+ MemTxResult res;\n+\n+ if (!FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID) ||\n+ !cfg->structure) {\n+ /* WI if no IST set up or it is not 2-level */\n+ return;\n+ }\n+\n+ /* Find the relevant L1 ISTE and set its VALID bit */\n+ l1_addr = l1_iste_addr(cs, cfg, intid);\n+\n+ l1_iste = address_space_ldq_le(&cs->dma_as, l1_addr, cfg->txattrs, &res);\n+ if (res != MEMTX_OK) {\n+ goto txfail;\n+ }\n+\n+ l1_iste = FIELD_DP64(l1_iste, L1_ISTE, VALID, 1);\n+\n+ address_space_stq_le(&cs->dma_as, l1_addr, l1_iste, cfg->txattrs, &res);\n+ if (res != MEMTX_OK) {\n+ goto txfail;\n+ }\n+ return;\n+\n+txfail:\n+ /* Reportable with EC=0x0 if sw error reporting implemented */\n+ qemu_log_mask(LOG_GUEST_ERROR, \"L1 ISTE update failed for ID 0x%x at \"\n+ \"physical address 0x\" HWADDR_FMT_plx \"\\n\", intid, l1_addr);\n+}\n+\n static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t value)\n {\n GICv5Common *cs = ARM_GICV5_COMMON(s);\n@@ -683,6 +720,9 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset,\n cs->irs_ist_cfgr[domain] = data;\n }\n return true;\n+ case A_IRS_MAP_L2_ISTR:\n+ irs_map_l2_istr_write(s, domain, data);\n+ return true;\n }\n \n return false;\n", "prefixes": [ "v2", "20/65" ] }