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GET /api/patches/2216880/?format=api
{ "id": 2216880, "url": "http://patchwork.ozlabs.org/api/patches/2216880/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-43-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-43-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:37", "name": "[v2,42/65] target/arm: GICv5 cpuif: Calculate the highest priority PPI", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "155ea365cf072e5637083ae0a5cf51ceb165a829", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-43-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216880/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216880/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=CZ9uepkd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhypV3jPYz1y1x\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:19:30 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65CJ-00076o-Or; Fri, 27 Mar 2026 07:17:51 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CF-00073k-6U\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:47 -0400", "from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CB-0008Ii-Sx\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:46 -0400", "by mail-wm1-x32d.google.com with SMTP id\n 5b1f17b1804b1-486b96760easo22060375e9.2\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:43 -0700 (PDT)", "from lanath.. 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helo=mail-wm1-x32d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "When the state of PPIs changes, recalculate the highest priority PPI.\nIn subsequent commits we will use this cached value to provide the\nHPPI info to the guest, decide whether to signal IRQ or FIQ, handle\ninterrupt acknowldge from the guest, and so on.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n include/hw/intc/arm_gicv5_types.h | 21 +++++++++++\n meson.build | 1 +\n target/arm/cpu.h | 3 ++\n target/arm/tcg/gicv5-cpuif.c | 58 +++++++++++++++++++++++++++++++\n target/arm/tcg/trace-events | 5 +++\n target/arm/tcg/trace.h | 1 +\n 6 files changed, 89 insertions(+)\n create mode 100644 target/arm/tcg/trace-events\n create mode 100644 target/arm/tcg/trace.h", "diff": "diff --git a/include/hw/intc/arm_gicv5_types.h b/include/hw/intc/arm_gicv5_types.h\nindex 5966ebde05..eaed42f49f 100644\n--- a/include/hw/intc/arm_gicv5_types.h\n+++ b/include/hw/intc/arm_gicv5_types.h\n@@ -12,6 +12,8 @@\n #ifndef HW_INTC_ARM_GICv5_TYPES_H\n #define HW_INTC_ARM_GICv5_TYPES_H\n \n+#include \"hw/core/registerfields.h\"\n+\n /*\n * The GICv5 has four physical Interrupt Domains. This numbering must\n * match the encoding used in IRS_IDR0.INT_DOM.\n@@ -86,4 +88,23 @@ typedef enum GICv5TriggerMode {\n \n #define PRIO_IDLE 0xff\n \n+/*\n+ * We keep track of candidate highest possible pending interrupts\n+ * using this struct.\n+ *\n+ * Unlike GICv3, we don't need a separate NMI bool, because for GICv5\n+ * superpriority is signaled by @prio == 0.\n+ *\n+ * In this struct the intid includes the interrupt type in bits\n+ * [31:29] (i.e. it is in the form defined by R_TJPHS).\n+ */\n+typedef struct GICv5PendingIrq {\n+ uint32_t intid;\n+ uint8_t prio;\n+} GICv5PendingIrq;\n+\n+/* Fields in a generic 32-bit INTID, per R_TJPHS */\n+FIELD(INTID, ID, 0, 24)\n+FIELD(INTID, TYPE, 29, 3)\n+\n #endif\ndiff --git a/meson.build b/meson.build\nindex d7c4095b39..85a3ab293f 100644\n--- a/meson.build\n+++ b/meson.build\n@@ -3684,6 +3684,7 @@ if have_system or have_user\n 'hw/core',\n 'target/arm',\n 'target/arm/hvf',\n+ 'target/arm/tcg',\n 'target/hppa',\n 'target/i386',\n 'target/i386/kvm',\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 6841b6748f..e0a7d02386 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -612,6 +612,9 @@ typedef struct CPUArchState {\n uint64_t ppi_enable[GICV5_NUM_PPIS / 64];\n /* The PRIO regs have 1 byte per PPI, so 8 PPIs to a register */\n uint64_t ppi_priority[GICV5_NUM_PPIS / 8];\n+\n+ /* Cached highest-priority pending PPI for each domain */\n+ GICv5PendingIrq ppi_hppi[NUM_GICV5_DOMAINS];\n } gicv5_cpuif;\n \n struct {\ndiff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 33e4762ef4..6f8062ba17 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -11,6 +11,7 @@\n #include \"internals.h\"\n #include \"cpregs.h\"\n #include \"hw/intc/arm_gicv5_stream.h\"\n+#include \"trace.h\"\n \n FIELD(GIC_CDPRI, ID, 0, 24)\n FIELD(GIC_CDPRI, TYPE, 29, 3)\n@@ -105,6 +106,57 @@ static uint64_t gic_running_prio(CPUARMState *env, GICv5Domain domain)\n return hap < 32 ? hap : PRIO_IDLE;\n }\n \n+static void gic_recalc_ppi_hppi(CPUARMState *env)\n+{\n+ /*\n+ * Recalculate the HPPI PPI: this is the best PPI which is\n+ * enabled, pending and not active.\n+ */\n+ for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_hppi); i++) {\n+ env->gicv5_cpuif.ppi_hppi[i].intid = 0;\n+ env->gicv5_cpuif.ppi_hppi[i].prio = PRIO_IDLE;\n+ };\n+\n+ for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_active); i++) {\n+ uint64_t en_pend_nact = env->gicv5_cpuif.ppi_enable[i] &\n+ env->gicv5_cpuif.ppi_pend[i] &\n+ ~env->gicv5_cpuif.ppi_active[i];\n+\n+ while (en_pend_nact) {\n+ /*\n+ * When EL3 is supported ICC_PPI_DOMAINR<n>_EL3 tells us\n+ * the domain of each PPI. While we only support EL1, the\n+ * domain is always NS.\n+ */\n+ GICv5Domain ppi_domain = GICV5_ID_NS;\n+ uint8_t prio;\n+ int ppi;\n+ int bit = ctz64(en_pend_nact);\n+\n+ en_pend_nact &= ~(1 << bit);\n+\n+ ppi = i * 64 + bit;\n+ prio = extract64(env->gicv5_cpuif.ppi_priority[ppi / 8],\n+ (ppi & 7) * 8, 5);\n+\n+ if (prio < env->gicv5_cpuif.ppi_hppi[ppi_domain].prio) {\n+ uint32_t intid = 0;\n+\n+ intid = FIELD_DP32(intid, INTID, ID, ppi);\n+ intid = FIELD_DP32(intid, INTID, TYPE, GICV5_PPI);\n+ env->gicv5_cpuif.ppi_hppi[ppi_domain].intid = intid;\n+ env->gicv5_cpuif.ppi_hppi[ppi_domain].prio = prio;\n+ }\n+ }\n+ }\n+\n+ for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.ppi_hppi); i++) {\n+ trace_gicv5_recalc_ppi_hppi(i,\n+ env->gicv5_cpuif.ppi_hppi[i].intid,\n+ env->gicv5_cpuif.ppi_hppi[i].prio);\n+ }\n+}\n+\n static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri,\n uint64_t value)\n {\n@@ -200,6 +252,7 @@ static void gic_ppi_cactive_write(CPUARMState *env, const ARMCPRegInfo *ri,\n {\n uint64_t old = raw_read(env, ri);\n raw_write(env, ri, old & ~value);\n+ gic_recalc_ppi_hppi(env);\n }\n \n static void gic_ppi_sactive_write(CPUARMState *env, const ARMCPRegInfo *ri,\n@@ -207,6 +260,7 @@ static void gic_ppi_sactive_write(CPUARMState *env, const ARMCPRegInfo *ri,\n {\n uint64_t old = raw_read(env, ri);\n raw_write(env, ri, old | value);\n+ gic_recalc_ppi_hppi(env);\n }\n \n static void gic_ppi_cpend_write(CPUARMState *env, const ARMCPRegInfo *ri,\n@@ -217,6 +271,7 @@ static void gic_ppi_cpend_write(CPUARMState *env, const ARMCPRegInfo *ri,\n uint64_t hm = env->gicv5_cpuif.ppi_hm[ri->opc2 & 1];\n value &= ~hm;\n raw_write(env, ri, old & ~value);\n+ gic_recalc_ppi_hppi(env);\n }\n \n static void gic_ppi_spend_write(CPUARMState *env, const ARMCPRegInfo *ri,\n@@ -227,18 +282,21 @@ static void gic_ppi_spend_write(CPUARMState *env, const ARMCPRegInfo *ri,\n uint64_t hm = env->gicv5_cpuif.ppi_hm[ri->opc2 & 1];\n value &= ~hm;\n raw_write(env, ri, old | value);\n+ gic_recalc_ppi_hppi(env);\n }\n \n static void gic_ppi_enable_write(CPUARMState *env, const ARMCPRegInfo *ri,\n uint64_t value)\n {\n raw_write(env, ri, value);\n+ gic_recalc_ppi_hppi(env);\n }\n \n static void gic_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *ri,\n uint64_t value)\n {\n raw_write(env, ri, value);\n+ gic_recalc_ppi_hppi(env);\n }\n \n /*\ndiff --git a/target/arm/tcg/trace-events b/target/arm/tcg/trace-events\nnew file mode 100644\nindex 0000000000..7dc5f781c5\n--- /dev/null\n+++ b/target/arm/tcg/trace-events\n@@ -0,0 +1,5 @@\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+# See docs/devel/tracing.rst for syntax documentation.\n+\n+# gicv5-cpuif.c\n+gicv5_recalc_ppi_hppi(int domain, uint32_t id, uint8_t prio) \"domain %d new PPI HPPI id 0x%x prio %u\"\ndiff --git a/target/arm/tcg/trace.h b/target/arm/tcg/trace.h\nnew file mode 100644\nindex 0000000000..c6e89d018b\n--- /dev/null\n+++ b/target/arm/tcg/trace.h\n@@ -0,0 +1 @@\n+#include \"trace/trace-target_arm_tcg.h\"\n", "prefixes": [ "v2", "42/65" ] }