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GET /api/patches/2216897/?format=api
{ "id": 2216897, "url": "http://patchwork.ozlabs.org/api/patches/2216897/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-42-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-42-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:36", "name": "[v2,41/65] target/arm: GICv5 cpuif: Implement ICC_APR_EL1 and ICC_HAPR_EL1", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9d52cfa305dd6ea6cb51fafd0967556471369eb0", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-42-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216897/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216897/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=I/osg9Dr;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhysB204Fz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:21:50 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65CH-00076A-NY; Fri, 27 Mar 2026 07:17:49 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CD-00071u-Hg\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:45 -0400", "from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CB-0008Go-8C\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:45 -0400", "by mail-wr1-x42a.google.com with SMTP id\n ffacd0b85a97d-439fe4985efso1507656f8f.3\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:42 -0700 (PDT)", "from lanath.. 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Since the GICv5 always uses 5 bits of priority, this\nregister always has 32 non-RES0 bits, and we don't need the\ncomplicated GICv3 setup where there might be 1, 2 or 4 APR registers.\n\nICC_HAPR_EL1 is a read-only register which reports the current\nrunning priority. This is defined to be the lowest set bit (i.e.\nthe highest priority) in the APR, or the Idle priority 0xff if there\nare no active interrupts, so it is effectively a convenience\nre-presentation of the APR register data.\n\nThe APR register is banked per interrupt domain; ICC_APR_EL1 accesses\nthe version of the register corresponding to the current logical\ninterrupt domain. The APR data for the final domain (EL3) is\naccessed via ICC_APR_EL3. Although we are starting with an EL1-only\nimplementation, we define the CPU state as banked here so we don't\nhave to change our representation of it later when we add EL3 and RME\nsupport.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n include/hw/intc/arm_gicv5_types.h | 2 ++\n target/arm/cpu.h | 2 ++\n target/arm/tcg/gicv5-cpuif.c | 60 +++++++++++++++++++++++++++++++\n 3 files changed, 64 insertions(+)", "diff": "diff --git a/include/hw/intc/arm_gicv5_types.h b/include/hw/intc/arm_gicv5_types.h\nindex f6f8709a6a..5966ebde05 100644\n--- a/include/hw/intc/arm_gicv5_types.h\n+++ b/include/hw/intc/arm_gicv5_types.h\n@@ -84,4 +84,6 @@ typedef enum GICv5TriggerMode {\n GICV5_TRIGGER_LEVEL = 1,\n } GICv5TriggerMode;\n \n+#define PRIO_IDLE 0xff\n+\n #endif\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex b97f659352..6841b6748f 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -35,6 +35,7 @@\n #include \"target/arm/gtimer.h\"\n #include \"target/arm/cpu-sysregs.h\"\n #include \"target/arm/mmuidx.h\"\n+#include \"hw/intc/arm_gicv5_types.h\"\n \n #define EXCP_UDEF 1 /* undefined instruction */\n #define EXCP_SWI 2 /* software interrupt */\n@@ -603,6 +604,7 @@ typedef struct CPUArchState {\n struct {\n /* GICv5 CPU interface data */\n uint64_t icc_icsr_el1;\n+ uint64_t icc_apr[NUM_GICV5_DOMAINS];\n /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register */\n uint64_t ppi_active[GICV5_NUM_PPIS / 64];\n uint64_t ppi_hm[GICV5_NUM_PPIS / 64];\ndiff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 74132ca097..33e4762ef4 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -95,6 +95,16 @@ static GICv5Domain gicv5_current_phys_domain(CPUARMState *env)\n return gicv5_logical_domain(env);\n }\n \n+static uint64_t gic_running_prio(CPUARMState *env, GICv5Domain domain)\n+{\n+ /*\n+ * Return the current running priority; this is the lowest set bit in\n+ * the Active Priority Register, or the idle priority if none (D_XMBQZ)\n+ */\n+ uint64_t hap = ctz64(env->gicv5_cpuif.icc_apr[domain]);\n+ return hap < 32 ? hap : PRIO_IDLE;\n+}\n+\n static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri,\n uint64_t value)\n {\n@@ -231,6 +241,44 @@ static void gic_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *ri,\n raw_write(env, ri, value);\n }\n \n+/*\n+ * ICC_APR_EL1 is banked and reads/writes as the version for the\n+ * current logical interrupt domain.\n+ */\n+static void gic_icc_apr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ /*\n+ * With an architectural 5 bits of priority, this register has 32\n+ * non-RES0 bits\n+ */\n+ GICv5Domain domain = gicv5_logical_domain(env);\n+ value &= 0xffffffff;\n+ env->gicv5_cpuif.icc_apr[domain] = value;\n+}\n+\n+static uint64_t gic_icc_apr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)\n+{\n+ GICv5Domain domain = gicv5_logical_domain(env);\n+ return env->gicv5_cpuif.icc_apr[domain];\n+}\n+\n+static void gic_icc_apr_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri)\n+{\n+ for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.icc_apr); i++) {\n+ env->gicv5_cpuif.icc_apr[i] = 0;\n+ }\n+}\n+\n+static uint64_t gic_icc_hapr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)\n+{\n+ /*\n+ * ICC_HAPR_EL1 reports the current running priority, which can be\n+ * calculated from the APR register.\n+ */\n+ return gic_running_prio(env, gicv5_current_phys_domain(env));\n+}\n+\n static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n /*\n * Barrier: wait until the effects of a cpuif system register\n@@ -382,6 +430,18 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]),\n .writefn = gic_ppi_spend_write,\n },\n+ { .name = \"ICC_APR_EL1\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 0,\n+ .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .readfn = gic_icc_apr_el1_read,\n+ .writefn = gic_icc_apr_el1_write,\n+ .resetfn = gic_icc_apr_el1_reset,\n+ },\n+ { .name = \"ICC_HAPR_EL1\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 3,\n+ .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .readfn = gic_icc_hapr_el1_read, .raw_writefn = arm_cp_write_ignore,\n+ },\n };\n \n void define_gicv5_cpuif_regs(ARMCPU *cpu)\n", "prefixes": [ "v2", "41/65" ] }