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GET /api/patches/2216914/?format=api
{ "id": 2216914, "url": "http://patchwork.ozlabs.org/api/patches/2216914/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-65-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-65-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:59", "name": "[v2,64/65] hw/arm/virt: Enable GICv5 CPU interface when using GICv5", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4dc91a7a7619edfc7774e6d09b42f56e3d4af7b8", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-65-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216914/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216914/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=jBJfJM+c;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyvD5Yw8z1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:23:36 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Dw-0002PI-Ef; Fri, 27 Mar 2026 07:19:32 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Ca-0007iq-29\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:08 -0400", "from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CX-0000Hw-Qo\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:07 -0400", "by mail-wr1-x42b.google.com with SMTP id\n ffacd0b85a97d-439b2965d4bso1507145f8f.2\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:18:04 -0700 (PDT)", "from lanath.. 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helo=mail-wr1-x42b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "If we are using the GICv5 in the virt board, we need to set the\nhas_gcie property on the CPU objects to tell them to implement the\ncpu interface part of GICv5.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/arm/virt.c | 8 ++++++++\n 1 file changed, 8 insertions(+)", "diff": "diff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex 15d833ad8f..0aff58bc3c 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -2675,6 +2675,14 @@ static void machvirt_init(MachineState *machine)\n object_property_set_bool(cpuobj, \"lpa2\", false, NULL);\n }\n \n+ if (vms->gic_version == VIRT_GIC_VERSION_5) {\n+ if (!object_property_find(cpuobj, \"has_gcie\")) {\n+ error_report(\"Using GICv5 but guest CPU does not support it\");\n+ exit(1);\n+ }\n+ object_property_set_bool(cpuobj, \"has_gcie\", true, NULL);\n+ }\n+\n if (object_property_find(cpuobj, \"reset-cbar\")) {\n object_property_set_int(cpuobj, \"reset-cbar\",\n vms->memmap[VIRT_CPUPERIPHS].base,\n", "prefixes": [ "v2", "64/65" ] }