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GET /api/patches/2216915/?format=api
{ "id": 2216915, "url": "http://patchwork.ozlabs.org/api/patches/2216915/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-27-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-27-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:21", "name": "[v2,26/65] target/arm: GICv5 cpuif: Implement GIC CDRCFG and ICC_ICSR_EL1", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3988414ee8925f362a89ee09663649361d1ca923", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-27-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216915/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216915/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=nYZ9uouy;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyvG6xmFz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:23:38 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65C4-0006oV-6a; Fri, 27 Mar 2026 07:17:36 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C2-0006m2-2y\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:34 -0400", "from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bw-0007yS-KD\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:33 -0400", "by mail-wr1-x42b.google.com with SMTP id\n ffacd0b85a97d-439b9b190easo1387511f8f.2\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:28 -0700 (PDT)", "from lanath.. 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Instead we will do migration via a GICv5 cpuif vmstate\nsection. This is necessary because some of the cpuif registers are\nbanked by interrupt domain and so need special handling to migrate\nthe data in all the banks; it's also how we handle the gicv3 cpuif\nregisters. (We expect that KVM also will expose the cpuif registers\nvia GIC-specific ioctls rather than as generic sysregs.) We'll mark\nall the GICv5 sysregs as NO_RAW.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/cpu.h | 5 +++++\n target/arm/tcg/gicv5-cpuif.c | 27 +++++++++++++++++++++++++++\n 2 files changed, 32 insertions(+)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 16de0ebfa8..1fdfd91ba4 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -597,6 +597,11 @@ typedef struct CPUArchState {\n uint64_t vmecid_a_el2;\n } cp15;\n \n+ struct {\n+ /* GICv5 CPU interface data */\n+ uint64_t icc_icsr_el1;\n+ } gicv5_cpuif;\n+\n struct {\n /* M profile has up to 4 stack pointers:\n * a Main Stack Pointer and a Process Stack Pointer for each\ndiff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 0c4349f8a7..8cf09791c1 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -35,6 +35,9 @@ FIELD(GIC_CDHM, ID, 0, 24)\n FIELD(GIC_CDHM, TYPE, 29, 3)\n FIELD(GIC_CDHM, HM, 32, 1)\n \n+FIELD(GIC_CDRCFG, ID, 0, 24)\n+FIELD(GIC_CDRCFG, TYPE, 29, 3)\n+\n static GICv5Common *gicv5_get_gic(CPUARMState *env)\n {\n return env->gicv5state;\n@@ -134,6 +137,19 @@ static void gic_cdpend_write(CPUARMState *env, const ARMCPRegInfo *ri,\n gicv5_set_pending(gic, id, pending, domain, type, virtual);\n }\n \n+static void gic_cdrcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ GICv5Common *gic = gicv5_get_gic(env);\n+ GICv5IntType type = FIELD_EX64(value, GIC_CDRCFG, TYPE);\n+ uint32_t id = FIELD_EX64(value, GIC_CDRCFG, ID);\n+ bool virtual = false;\n+ GICv5Domain domain = gicv5_current_phys_domain(env);\n+\n+ env->gicv5_cpuif.icc_icsr_el1 =\n+ gicv5_request_config(gic, id, domain, type, virtual);\n+}\n+\n static void gic_cdhm_write(CPUARMState *env, const ARMCPRegInfo *ri,\n uint64_t value)\n {\n@@ -194,11 +210,22 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n .writefn = gic_cdpend_write,\n },\n+ { .name = \"GIC_CDRCFG\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 5,\n+ .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .writefn = gic_cdrcfg_write,\n+ },\n { .name = \"GIC_CDHM\", .state = ARM_CP_STATE_AA64,\n .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 2, .opc2 = 1,\n .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n .writefn = gic_cdhm_write,\n },\n+ { .name = \"ICC_ICSR_EL1\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 4,\n+ .access = PL1_RW, .type = ARM_CP_NO_RAW,\n+ .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.icc_icsr_el1),\n+ .resetvalue = 0,\n+ },\n };\n \n void define_gicv5_cpuif_regs(ARMCPU *cpu)\n", "prefixes": [ "v2", "26/65" ] }