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GET /api/patches/2216892/?format=api
{ "id": 2216892, "url": "http://patchwork.ozlabs.org/api/patches/2216892/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-48-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-48-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:42", "name": "[v2,47/65] hw/intc/arm_gicv5: Implement Activate command", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e60222acba4550a751da777d5cb8befe3d101604", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-48-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216892/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216892/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=IQT3bag1;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhys23xZKz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:21:42 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Cb-0007nY-E8; Fri, 27 Mar 2026 07:18:09 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CI-00076v-Rp\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:51 -0400", "from mail-wr1-x430.google.com ([2a00:1450:4864:20::430])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CG-0008Nc-7q\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:50 -0400", "by mail-wr1-x430.google.com with SMTP id\n ffacd0b85a97d-43b95e5b3afso1067303f8f.3\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:47 -0700 (PDT)", "from lanath.. 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2026 11:16:42 +0000", "Message-ID": "<20260327111700.795099-48-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327111700.795099-1-peter.maydell@linaro.org>", "References": "<20260327111700.795099-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::430;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Implement the equivalent of the GICv5 stream protocol's Activate\ncommand, which lets the cpuif tell the IRS to move its current\nhighest priority pending interrupt into the Active state, and to\nclear the Pending state for an Edge handling mode interrupt.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5.c | 58 ++++++++++++++++++++++++++++++\n hw/intc/trace-events | 1 +\n include/hw/intc/arm_gicv5_stream.h | 23 ++++++++++++\n 3 files changed, 82 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex 605cf6fd6f..942f3eba2e 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -1095,6 +1095,64 @@ uint64_t gicv5_request_config(GICv5Common *cs, uint32_t id, GICv5Domain domain,\n }\n }\n \n+void gicv5_activate(GICv5Common *cs, uint32_t id, GICv5Domain domain,\n+ GICv5IntType type, bool virtual)\n+{\n+ GICv5 *s = ARM_GICV5(cs);\n+ uint32_t iaffid;\n+\n+ trace_gicv5_activate(domain_name[domain], inttype_name(type), virtual, id);\n+\n+ if (virtual) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_activate: tried to \"\n+ \"activate a virtual interrupt\\n\");\n+ return;\n+ }\n+\n+ switch (type) {\n+ case GICV5_LPI:\n+ {\n+ const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain];\n+ L2_ISTE_Handle h;\n+ uint32_t *l2_iste_p = get_l2_iste(cs, cfg, id, &h);\n+\n+ if (!l2_iste_p) {\n+ return;\n+ }\n+ *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, ACTIVE, true);\n+ if (FIELD_EX32(*l2_iste_p, L2_ISTE, HM) == GICV5_EDGE) {\n+ *l2_iste_p = FIELD_DP32(*l2_iste_p, L2_ISTE, PENDING, false);\n+ }\n+ iaffid = FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID);\n+ put_l2_iste(cs, cfg, &h);\n+ break;\n+ }\n+ case GICV5_SPI:\n+ {\n+ GICv5SPIState *spi = gicv5_spi_state(cs, id, domain);\n+\n+ if (!spi) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_activate: tried to \"\n+ \"activate unreachable SPI %d\\n\", id);\n+ return;\n+ }\n+\n+ spi->active = true;\n+ if (spi->hm == GICV5_EDGE) {\n+ spi->pending = false;\n+ }\n+ iaffid = spi->iaffid;\n+ break;\n+ }\n+ default:\n+ qemu_log_mask(LOG_GUEST_ERROR, \"gicv5_activate: tried to \"\n+ \"activate bad interrupt type %d\\n\", type);\n+ return;\n+ }\n+\n+ irs_recalc_hppi(s, domain, iaffid);\n+}\n+\n static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t value)\n {\n GICv5Common *cs = ARM_GICV5_COMMON(s);\ndiff --git a/hw/intc/trace-events b/hw/intc/trace-events\nindex 6475ba5959..636c598970 100644\n--- a/hw/intc/trace-events\n+++ b/hw/intc/trace-events\n@@ -241,6 +241,7 @@ gicv5_set_pending(const char *domain, const char *type, bool virtual, uint32_t i\n gicv5_set_handling(const char *domain, const char *type, bool virtual, uint32_t id, int handling) \"GICv5 IRS SetHandling %s %s virtual:%d ID %u handling %d\"\n gicv5_set_target(const char *domain, const char *type, bool virtual, uint32_t id, uint32_t iaffid, int irm) \"GICv5 IRS SetTarget %s %s virtual:%d ID %u IAFFID %u routingmode %d\"\n gicv5_request_config(const char *domain, const char *type, bool virtual, uint32_t id, uint64_t icsr) \"GICv5 IRS RequestConfig %s %s virtual:%d ID %u ICSR 0x%\" PRIx64\n+gicv5_activate(const char *domain, const char *type, bool virtual, uint32_t id) \"GICv5 IRS Activate %s %s virtual:%d ID %u\"\n gicv5_spi_state(uint32_t spi_id, bool level, bool pending, bool active) \"GICv5 IRS SPI ID %u now level %d pending %d active %d\"\n gicv5_irs_recalc_hppi_fail(const char *domain, uint32_t iaffid, const char *reason) \"GICv5 IRS %s IAFFID %u: no HPPI: %s\"\n gicv5_irs_recalc_hppi(const char *domain, uint32_t iaffid, uint32_t id, uint8_t prio) \"GICv5 IRS %s IAFFID %u: new HPPI ID 0x%x prio %u\"\ndiff --git a/include/hw/intc/arm_gicv5_stream.h b/include/hw/intc/arm_gicv5_stream.h\nindex cc1c7cc438..7ac24f0f09 100644\n--- a/include/hw/intc/arm_gicv5_stream.h\n+++ b/include/hw/intc/arm_gicv5_stream.h\n@@ -151,6 +151,29 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, uint32_t iaffid,\n uint64_t gicv5_request_config(GICv5Common *cs, uint32_t id, GICv5Domain domain,\n GICv5IntType type, bool virtual);\n \n+/**\n+ * gicv5_activate\n+ * @cs: GIC IRS to send command to\n+ * @id: interrupt ID\n+ * @domain: interrupt domain to act on\n+ * @type: interrupt type (LPI or SPI)\n+ * @virtual: true if this is a virtual interrupt\n+ *\n+ * Activate the IRS's highest priority pending interrupt; matches the\n+ * stream interface's Activate command.\n+ *\n+ * In the stream interface, the command has only the domain and\n+ * virtual fields, because both the IRS and the CPUIF keep track of\n+ * the IRS's current HPPI. In QEMU, we also have arguments here for\n+ * @id and @type which are telling the IRS something that in hardware\n+ * it already knows. This is because we have them to hand in the cpuif\n+ * code, and it means we don't need to pass in an iaffid argument to\n+ * tell the IRS which CPU we are so it can find the right element in\n+ * its hppi[][] array.\n+ */\n+void gicv5_activate(GICv5Common *cs, uint32_t id, GICv5Domain domain,\n+ GICv5IntType type, bool virtual);\n+\n /**\n * gicv5_forward_interrupt\n * @cpu: CPU interface to forward interrupt to\n", "prefixes": [ "v2", "47/65" ] }