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GET /api/patches/2216926/?format=api
{ "id": 2216926, "url": "http://patchwork.ozlabs.org/api/patches/2216926/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-60-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-60-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:54", "name": "[v2,59/65] hw/arm/virt: Split GICv2 and GICv3/4 creation", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8617c9226f61e9bf6fca0962d67c987403d26d42", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-60-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216926/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216926/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=jZ7by7kJ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyxc21WMz1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:25:40 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Dr-0001wQ-A2; Fri, 27 Mar 2026 07:19:27 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CY-0007Xu-3J\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:06 -0400", "from mail-wr1-x433.google.com ([2a00:1450:4864:20::433])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CT-0000AW-FM\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:04 -0400", "by mail-wr1-x433.google.com with SMTP id\n ffacd0b85a97d-439b9cf8cb5so1919646f8f.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:58 -0700 (PDT)", "from lanath.. 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GICv5 will be different to both.\n\nRefactor into create_gicv2() and create_gicv3().\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/arm/virt.c | 137 ++++++++++++++++++++++++++++++--------------------\n 1 file changed, 82 insertions(+), 55 deletions(-)", "diff": "diff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex 5a2cb81919..8c383d7e40 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -861,26 +861,58 @@ static void gic_connect_ppis(VirtMachineState *vms)\n }\n }\n \n-static void create_gic(VirtMachineState *vms, MemoryRegion *mem)\n+static void create_gicv2(VirtMachineState *vms, MemoryRegion *mem)\n {\n MachineState *ms = MACHINE(vms);\n /* We create a standalone GIC */\n SysBusDevice *gicbusdev;\n- const char *gictype;\n unsigned int smp_cpus = ms->smp.cpus;\n- uint32_t nb_redist_regions = 0;\n- int revision;\n \n- if (vms->gic_version == VIRT_GIC_VERSION_2) {\n- gictype = gic_class_name();\n- } else {\n- gictype = gicv3_class_name();\n+ if (kvm_enabled() && vms->virt) {\n+ error_report(\"KVM EL2 is only supported with in-kernel GICv3\");\n+ exit(1);\n }\n \n+ vms->gic = qdev_new(gic_class_name());\n+ qdev_prop_set_uint32(vms->gic, \"revision\", 2);\n+ qdev_prop_set_uint32(vms->gic, \"num-cpu\", smp_cpus);\n+ /*\n+ * Note that the num-irq property counts both internal and external\n+ * interrupts; there are always 32 of the former (mandated by GIC spec).\n+ */\n+ qdev_prop_set_uint32(vms->gic, \"num-irq\", NUM_IRQS + 32);\n+ if (!kvm_irqchip_in_kernel()) {\n+ qdev_prop_set_bit(vms->gic, \"has-security-extensions\", vms->secure);\n+ qdev_prop_set_bit(vms->gic, \"has-virtualization-extensions\", vms->virt);\n+ }\n+\n+ gicbusdev = SYS_BUS_DEVICE(vms->gic);\n+ sysbus_realize_and_unref(gicbusdev, &error_fatal);\n+ sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);\n+ sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);\n+ if (vms->virt) {\n+ sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);\n+ sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);\n+ }\n+\n+ gic_connect_ppis(vms);\n+\n+ fdt_add_gic_node(vms);\n+}\n+\n+static void create_gicv3(VirtMachineState *vms, MemoryRegion *mem)\n+{\n+ MachineState *ms = MACHINE(vms);\n+ /* We create a standalone GIC */\n+ SysBusDevice *gicbusdev;\n+ unsigned int smp_cpus = ms->smp.cpus;\n+ uint32_t nb_redist_regions;\n+ int revision;\n+ QList *redist_region_count;\n+ uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST);\n+ uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);\n+\n switch (vms->gic_version) {\n- case VIRT_GIC_VERSION_2:\n- revision = 2;\n- break;\n case VIRT_GIC_VERSION_3:\n revision = 3;\n break;\n@@ -897,10 +929,11 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)\n exit(1);\n }\n \n- vms->gic = qdev_new(gictype);\n+ vms->gic = qdev_new(gicv3_class_name());\n qdev_prop_set_uint32(vms->gic, \"revision\", revision);\n qdev_prop_set_uint32(vms->gic, \"num-cpu\", smp_cpus);\n- /* Note that the num-irq property counts both internal and external\n+ /*\n+ * Note that the num-irq property counts both internal and external\n * interrupts; there are always 32 of the former (mandated by GIC spec).\n */\n qdev_prop_set_uint32(vms->gic, \"num-irq\", NUM_IRQS + 32);\n@@ -908,40 +941,28 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)\n qdev_prop_set_bit(vms->gic, \"has-security-extensions\", vms->secure);\n }\n \n- if (vms->gic_version != VIRT_GIC_VERSION_2) {\n- QList *redist_region_count;\n- uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST);\n- uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);\n+ nb_redist_regions = virt_gicv3_redist_region_count(vms);\n \n- nb_redist_regions = virt_gicv3_redist_region_count(vms);\n+ redist_region_count = qlist_new();\n+ qlist_append_int(redist_region_count, redist0_count);\n+ if (nb_redist_regions == 2) {\n+ uint32_t redist1_capacity =\n+ virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);\n \n- redist_region_count = qlist_new();\n- qlist_append_int(redist_region_count, redist0_count);\n- if (nb_redist_regions == 2) {\n- uint32_t redist1_capacity =\n- virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);\n+ qlist_append_int(redist_region_count,\n+ MIN(smp_cpus - redist0_count, redist1_capacity));\n+ }\n+ qdev_prop_set_array(vms->gic, \"redist-region-count\", redist_region_count);\n \n- qlist_append_int(redist_region_count,\n- MIN(smp_cpus - redist0_count, redist1_capacity));\n- }\n- qdev_prop_set_array(vms->gic, \"redist-region-count\",\n- redist_region_count);\n-\n- if (!kvm_irqchip_in_kernel()) {\n- if (vms->tcg_its) {\n- object_property_set_link(OBJECT(vms->gic), \"sysmem\",\n- OBJECT(mem), &error_fatal);\n- qdev_prop_set_bit(vms->gic, \"has-lpi\", true);\n- }\n- } else if (vms->virt) {\n- qdev_prop_set_uint32(vms->gic, \"maintenance-interrupt-id\",\n- ARCH_GIC_MAINT_IRQ);\n- }\n- } else {\n- if (!kvm_irqchip_in_kernel()) {\n- qdev_prop_set_bit(vms->gic, \"has-virtualization-extensions\",\n- vms->virt);\n+ if (!kvm_irqchip_in_kernel()) {\n+ if (vms->tcg_its) {\n+ object_property_set_link(OBJECT(vms->gic), \"sysmem\", OBJECT(mem),\n+ &error_fatal);\n+ qdev_prop_set_bit(vms->gic, \"has-lpi\", true);\n }\n+ } else if (vms->virt) {\n+ qdev_prop_set_uint32(vms->gic, \"maintenance-interrupt-id\",\n+ ARCH_GIC_MAINT_IRQ);\n }\n \n if (gicv3_nmi_present(vms)) {\n@@ -951,18 +972,9 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)\n gicbusdev = SYS_BUS_DEVICE(vms->gic);\n sysbus_realize_and_unref(gicbusdev, &error_fatal);\n sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);\n- if (vms->gic_version != VIRT_GIC_VERSION_2) {\n- sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);\n- if (nb_redist_regions == 2) {\n- sysbus_mmio_map(gicbusdev, 2,\n- vms->memmap[VIRT_HIGH_GIC_REDIST2].base);\n- }\n- } else {\n- sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);\n- if (vms->virt) {\n- sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);\n- sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);\n- }\n+ sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);\n+ if (nb_redist_regions == 2) {\n+ sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base);\n }\n \n gic_connect_ppis(vms);\n@@ -970,6 +982,21 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)\n fdt_add_gic_node(vms);\n }\n \n+static void create_gic(VirtMachineState *vms, MemoryRegion *mem)\n+{\n+ switch (vms->gic_version) {\n+ case VIRT_GIC_VERSION_2:\n+ create_gicv2(vms, mem);\n+ break;\n+ case VIRT_GIC_VERSION_3:\n+ case VIRT_GIC_VERSION_4:\n+ create_gicv3(vms, mem);\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+}\n+\n static void create_msi_controller(VirtMachineState *vms)\n {\n switch (vms->msi_controller) {\n", "prefixes": [ "v2", "59/65" ] }