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GET /api/patches/2216934/?format=api
{ "id": 2216934, "url": "http://patchwork.ozlabs.org/api/patches/2216934/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-50-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-50-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:44", "name": "[v2,49/65] target/arm: GICv5 cpuif: Implement GIC CDEOI", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "659e1da8e9de994136ee1f06b9d970fd18a0d8b0", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-50-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216934/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216934/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=k0qFlTXq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyyx6RJ7z1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:26:49 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65CV-0007SB-L2; Fri, 27 Mar 2026 07:18:05 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CJ-00077B-PK\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:51 -0400", "from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CI-0008Ph-33\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:51 -0400", "by mail-wr1-x42a.google.com with SMTP id\n ffacd0b85a97d-43b5bded412so1432698f8f.0\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:49 -0700 (PDT)", "from lanath.. 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helo=mail-wr1-x42a.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Implement the GIC CDEOI instruction, which performs a \"priority\ndrop\", clearing the highest set bit in the APR register.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/tcg/gicv5-cpuif.c | 21 +++++++++++++++++++++\n target/arm/tcg/trace-events | 1 +\n 2 files changed, 22 insertions(+)", "diff": "diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 09870e0b09..0974637c92 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -554,6 +554,22 @@ static uint64_t gicr_cdia_read(CPUARMState *env, const ARMCPRegInfo *ri)\n return hppi.intid | R_GICR_CDIA_VALID_MASK;\n }\n \n+static void gic_cdeoi_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ /*\n+ * Perform Priority Drop in the current interrupt domain.\n+ * This is just clearing the lowest set bit in the APR.\n+ */\n+ GICv5Domain domain = gicv5_current_phys_domain(env);\n+ uint64_t *apr = &env->gicv5_cpuif.icc_apr[domain];\n+\n+ trace_gicv5_cdeoi(domain);\n+\n+ /* clear lowest bit, doing nothing if already zero */\n+ *apr &= *apr - 1;\n+}\n+\n static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n /*\n * Barrier: wait until the effects of a cpuif system register\n@@ -606,6 +622,11 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n .writefn = gic_cdrcfg_write,\n },\n+ { .name = \"GIC_CDEOI\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 7,\n+ .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .writefn = gic_cdeoi_write,\n+ },\n { .name = \"GIC_CDHM\", .state = ARM_CP_STATE_AA64,\n .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 2, .opc2 = 1,\n .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\ndiff --git a/target/arm/tcg/trace-events b/target/arm/tcg/trace-events\nindex 13e15cfcfc..fcb3106a96 100644\n--- a/target/arm/tcg/trace-events\n+++ b/target/arm/tcg/trace-events\n@@ -5,3 +5,4 @@\n gicv5_recalc_ppi_hppi(int domain, uint32_t id, uint8_t prio) \"domain %d new PPI HPPI id 0x%x prio %u\"\n gicv5_gicr_cdia_fail(int domain, const char *reason) \"domain %d CDIA attempt failed: %s\"\n gicv5_gicr_cdia(int domain, uint32_t id) \"domain %d CDIA acknowledge of interrupt 0x%x\"\n+gicv5_cdeoi(int domain) \"domain %d CDEOI performing priority drop\"\n", "prefixes": [ "v2", "49/65" ] }