Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2216893/?format=api
{ "id": 2216893, "url": "http://patchwork.ozlabs.org/api/patches/2216893/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-52-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-52-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:46", "name": "[v2,51/65] target/arm: GICv5 cpuif: Implement GIC CDDI", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a442463db2993e944b2a992219794ea1b5fbfc1d", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-52-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216893/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216893/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Jp4xcvqA;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhys44M1sz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:21:44 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65D6-0008NW-PD; Fri, 27 Mar 2026 07:18:44 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CL-0007D9-Nu\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:55 -0400", "from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CJ-0008Qr-Rq\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:53 -0400", "by mail-wr1-x42b.google.com with SMTP id\n ffacd0b85a97d-43b88b7ca76so1564198f8f.3\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:51 -0700 (PDT)", "from lanath.. (wildly.archaic.org.uk. [81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.49\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 27 Mar 2026 04:17:49 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1774610270; x=1775215070; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=2JOiLlKzr2TVNV+HAOZ57k8l0kQLTn+WAmtWxV5Vt4w=;\n b=Jp4xcvqAOdxLeEgAVvzTEP9uw0X7h36D6IY14yIoa2taEx3db9qek2pcQBjuw4QWov\n UMLN8GAbisHSz2l/EFbui48ckMw+I7HyGzdSLndxUnS8pSK4NbZlfW8gyo5gnFWWkY5a\n gkr2IJj03d8XWTWPnbk0EIqZd6Y02GGjRU1A2VM+XSyL0YExPo/cSW+/mAEEqd9LaPM+\n Ghz5zG2+kpV/EcxfllbqJJ7EQRcCtMFkSaypGUMT+7C9WbfKEF6WyeQq+9KO+geb2Prv\n lo/bG+zC1VWYQEhD0GDUYMBAXGs/3/wshr1akDdOqak3ZyRMhpHO3Uk9Y7glrqCYs1Ur\n Oe6w==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774610270; x=1775215070;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=2JOiLlKzr2TVNV+HAOZ57k8l0kQLTn+WAmtWxV5Vt4w=;\n b=UUkqlqXaQEPYnW7ItX/JQRsyfXzaWDelKGVackbs8yD3brLGITXK47U+DjXlq/E8yi\n SmBw72IuXxW4IJA80YdEZTEGGf0WFKNYk/NQcypw8a/M9Hxh2/no+Df/WjPeRVGHhZYN\n 8efjFOXSDYETASYkbBcU8FnuVLbP+lEak/4vNaGJ0pWGCz4cSuebXDDDFRxAS+GTMJJk\n 1fKUNgKpIP14gcN7NdOkDvnV2qs/rPmZ3l84NvchFzgn46sDJVKfJRFAqKN2yB7aMJlD\n 1yOFsjsADXF8b09l4rd27TJQkTvTXdtWI/fCQV94sktnvsWmIzr/I7ueE2EVLVw9SIVC\n 5WSg==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCVFOmE5EzqVfrPxJBo9qnpcmKCNgwoZTN6CTKT9bJIfVuARdGgTt1nWxiLWRGEEfg0Q2w2DD4mISXEf@nongnu.org", "X-Gm-Message-State": "AOJu0YyRems4fUQSD6fRNRoO3f1n1COmMrxeu5XtG67sYRlwtaoHr/AQ\n xo1uXEB/wnpkiFoJSqvdB66NaDMKJiThVQEZxPd7TUP3dcldtukBx5Fo750L0t1/CPY=", "X-Gm-Gg": "ATEYQzzt8G1+1lNUye+cThMj8Weej48gyuCsMZdVWDWyU0dwqd9HFmCda5wf0ooWl7P\n 5Q65DlhrZOKqh5fYf8vETb6aRo7Pw28vWveWOfZEuIzlCdwHwLt6jkPJtPSBGJEUmaG1AaXk3t2\n IUs05W6EG6/Dpc1cFEVIebQJZ5j2YyBsi4PYiEI9xXZWUr1KXBCLJWgjr+tbZKwKVHToOzygl1L\n Dm2T3j7Me2OUCgCIjnWLyMa41dtVFzUKE06eaBQjmSukthf9slLcs+y/qjuWg7ZXoifzJASazOV\n P1cV9FlGTHlvag1KPgOe5QpB034mwfyeHz+oC4NsoKeFfPJj3MFbiiKCWhaEaE0o1ZP75TIo48c\n tAaGlxJ+oOzxpa7WQ6cu1w2BcrzK4cqMP8QNAsCC3FbVdiHnBluigaikjlSJN0uLdFutB1PLrmE\n CjAf5aVqetuYcLG76/pXPFUcrS15BfYQil2PBubDTvEX+zrNzO1rsfJSYDLrlMX1KnCjGxFdaOz\n eNO8RtrfCXyjZNqZJsAKmY2K45O25g=", "X-Received": "by 2002:a5d:5d10:0:b0:439:ae2a:755e with SMTP id\n ffacd0b85a97d-43b9e9a9785mr3446297f8f.23.1774610270251;\n Fri, 27 Mar 2026 04:17:50 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Jonathan Cameron <jonathan.cameron@huawei.com>", "Subject": "[PATCH v2 51/65] target/arm: GICv5 cpuif: Implement GIC CDDI", "Date": "Fri, 27 Mar 2026 11:16:46 +0000", "Message-ID": "<20260327111700.795099-52-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327111700.795099-1-peter.maydell@linaro.org>", "References": "<20260327111700.795099-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::42b;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Implement the GIC CDDI system instruction, which deactivates the\nspecified interrupt.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/tcg/gicv5-cpuif.c | 49 ++++++++++++++++++++++++++++++++++++\n target/arm/tcg/trace-events | 1 +\n 2 files changed, 50 insertions(+)", "diff": "diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 0974637c92..94590bd765 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -17,6 +17,9 @@ FIELD(GIC_CDPRI, ID, 0, 24)\n FIELD(GIC_CDPRI, TYPE, 29, 3)\n FIELD(GIC_CDPRI, PRIORITY, 35, 5)\n \n+FIELD(GIC_CDDI, ID, 0, 24)\n+FIELD(GIC_CDDI, TYPE, 29, 3)\n+\n FIELD(GIC_CDDIS, ID, 0, 24)\n FIELD(GIC_CDDIS, TYPE, 29, 3)\n \n@@ -570,6 +573,47 @@ static void gic_cdeoi_write(CPUARMState *env, const ARMCPRegInfo *ri,\n *apr &= *apr - 1;\n }\n \n+static void gic_cddi_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ /*\n+ * Clear the Active state of the specified interrupt in the\n+ * current interrupt domain.\n+ */\n+ GICv5Common *gic = gicv5_get_gic(env);\n+ GICv5Domain domain = gicv5_current_phys_domain(env);\n+ GICv5IntType type = FIELD_EX64(value, GIC_CDDI, TYPE);\n+ uint32_t id = FIELD_EX64(value, GIC_CDDI, ID);\n+ bool virtual = false;\n+\n+ trace_gicv5_cddi(domain, value);\n+\n+ switch (type) {\n+ case GICV5_PPI:\n+ {\n+ uint32_t ppireg, ppibit;\n+\n+ if (id >= GICV5_NUM_PPIS) {\n+ break;\n+ }\n+\n+ ppireg = id / 64;\n+ ppibit = 1 << (id % 64);\n+\n+ env->gicv5_cpuif.ppi_active[ppireg] &= ~ppibit;\n+ gic_recalc_ppi_hppi(env);\n+ break;\n+ }\n+ case GICV5_LPI:\n+ case GICV5_SPI:\n+ /* Tell the IRS to deactivate this interrupt */\n+ gicv5_deactivate(gic, id, domain, type, virtual);\n+ break;\n+ default:\n+ break;\n+ }\n+}\n+\n static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n /*\n * Barrier: wait until the effects of a cpuif system register\n@@ -627,6 +671,11 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n .writefn = gic_cdeoi_write,\n },\n+ { .name = \"GIC_CDDI\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 2, .opc2 = 0,\n+ .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .writefn = gic_cddi_write,\n+ },\n { .name = \"GIC_CDHM\", .state = ARM_CP_STATE_AA64,\n .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 2, .opc2 = 1,\n .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\ndiff --git a/target/arm/tcg/trace-events b/target/arm/tcg/trace-events\nindex fcb3106a96..c60ce6834e 100644\n--- a/target/arm/tcg/trace-events\n+++ b/target/arm/tcg/trace-events\n@@ -6,3 +6,4 @@ gicv5_recalc_ppi_hppi(int domain, uint32_t id, uint8_t prio) \"domain %d new PPI\n gicv5_gicr_cdia_fail(int domain, const char *reason) \"domain %d CDIA attempt failed: %s\"\n gicv5_gicr_cdia(int domain, uint32_t id) \"domain %d CDIA acknowledge of interrupt 0x%x\"\n gicv5_cdeoi(int domain) \"domain %d CDEOI performing priority drop\"\n+gicv5_cddi(int domain, uint32_t id) \"domain %d CDDI deactivating interrupt ID 0x%x\"\n", "prefixes": [ "v2", "51/65" ] }