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GET /api/patches/2216898/?format=api
{ "id": 2216898, "url": "http://patchwork.ozlabs.org/api/patches/2216898/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-20-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-20-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:14", "name": "[v2,19/65] target/arm: GICv5 cpuif: Implement the GIC CDPRI instruction", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f0bc167280a922b2760bf61acb8be6297e03b0d4", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-20-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216898/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216898/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=lpaPJ2ur;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhysD0ydqz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:21:52 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Bu-0006Zr-Oo; Fri, 27 Mar 2026 07:17:26 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Br-0006WC-Av\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:23 -0400", "from mail-wr1-x435.google.com ([2a00:1450:4864:20::435])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bp-0007vL-FH\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:23 -0400", "by mail-wr1-x435.google.com with SMTP id\n ffacd0b85a97d-439b2965d4bso1506662f8f.2\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:20 -0700 (PDT)", "from lanath.. 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helo=mail-wr1-x435.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Implement the CPU interface GIC CDPRI instruction, which is a wrapper\naround the SetPriority operation.\n\nAs with the barrier insns, we omit for the moment details which are\nneeded when the GICv5 supports virtualization:\n\n * traps when legacy GICv3 emulation is enabled\n * fine-grained-trap handling (which is done via\n registers that are new in GICv5)\n * sending the command for the virtual interrupt domain\n when inside a guest\n\nThe CD instructions operate on the Current Physical Interrupt Domain,\nwhich is the one associated with the current security state and\nexception level. The spec also has the concept of a Logical\nInterrupt Domain, which is the one associated with the security state\ndefined by SCR_EL3.{NS,NSE}. Mostly the logical interrupt domain is\nused by the LD instructions, which are EL3-only; but we will also\nwant the concept later for handling some banked registers, so we\ndefine functions for both.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/tcg/gicv5-cpuif.c | 58 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 58 insertions(+)", "diff": "diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 7392a98c49..0c2bba5ce9 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -10,6 +10,59 @@\n #include \"cpu.h\"\n #include \"internals.h\"\n #include \"cpregs.h\"\n+#include \"hw/intc/arm_gicv5_stream.h\"\n+\n+FIELD(GIC_CDPRI, ID, 0, 24)\n+FIELD(GIC_CDPRI, TYPE, 29, 3)\n+FIELD(GIC_CDPRI, PRIORITY, 35, 5)\n+\n+static GICv5Common *gicv5_get_gic(CPUARMState *env)\n+{\n+ return env->gicv5state;\n+}\n+\n+static GICv5Domain gicv5_logical_domain(CPUARMState *env)\n+{\n+ /*\n+ * Return the Logical Interrupt Domain, which is the one associated\n+ * with the security state selected by the SCR_EL3.{NS,NSE} bits\n+ */\n+ switch (arm_security_space_below_el3(env)) {\n+ case ARMSS_Secure:\n+ return GICV5_ID_S;\n+ case ARMSS_NonSecure:\n+ return GICV5_ID_NS;\n+ case ARMSS_Realm:\n+ return GICV5_ID_REALM;\n+ default:\n+ g_assert_not_reached();\n+ }\n+}\n+\n+static GICv5Domain gicv5_current_phys_domain(CPUARMState *env)\n+{\n+ /*\n+ * Return the Current Physical Interrupt Domain as\n+ * defined by R_ZFCXM.\n+ */\n+ if (arm_current_el(env) == 3) {\n+ return GICV5_ID_EL3;\n+ }\n+ return gicv5_logical_domain(env);\n+}\n+\n+static void gic_cdpri_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ GICv5Common *gic = gicv5_get_gic(env);\n+ uint8_t priority = FIELD_EX64(value, GIC_CDPRI, PRIORITY);\n+ GICv5IntType type = FIELD_EX64(value, GIC_CDPRI, TYPE);\n+ uint32_t id = FIELD_EX64(value, GIC_CDPRI, ID);\n+ bool virtual = false;\n+ GICv5Domain domain = gicv5_current_phys_domain(env);\n+\n+ gicv5_set_priority(gic, id, priority, domain, type, virtual);\n+}\n \n static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n /*\n@@ -33,6 +86,11 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,\n .access = PL1_W, .type = ARM_CP_NOP,\n },\n+ { .name = \"GIC_CDPRI\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 2,\n+ .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .writefn = gic_cdpri_write,\n+ },\n };\n \n void define_gicv5_cpuif_regs(ARMCPU *cpu)\n", "prefixes": [ "v2", "19/65" ] }