Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2216925/?format=api
{ "id": 2216925, "url": "http://patchwork.ozlabs.org/api/patches/2216925/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-66-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-66-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:17:00", "name": "[v2,65/65] hw/arm/virt: Allow user to select GICv5", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ca2ea57ffc8e724ce348f8bc3da08e226df7410d", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-66-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216925/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216925/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=CQWhW8mx;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyxR4mjlz1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:25:31 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Dq-0001v1-Q7; Fri, 27 Mar 2026 07:19:27 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Cb-0007qV-Q1\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:09 -0400", "from mail-wr1-x431.google.com ([2a00:1450:4864:20::431])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CX-0000JY-Re\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:18:09 -0400", "by mail-wr1-x431.google.com with SMTP id\n ffacd0b85a97d-43b7481f9d3so1157578f8f.3\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:18:04 -0700 (PDT)", "from lanath.. (wildly.archaic.org.uk. [81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.18.03\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 27 Mar 2026 04:18:03 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1774610284; x=1775215084; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=9Sc6A8mUH5H33CEhbJhf4m2nOob0B+CIV382Sacc+zU=;\n b=CQWhW8mxpojBqTu4WsPGMT5aR6KideQbgdCncVkUgpeKqR6zEC946GZI3vVoaPgKW9\n LiHr5Wuy/qat/pjyN7vj1Z+i0vryOq7KOtTtf3dMFE3TV2m5VNzoLy6Njg+eXfLR+cIx\n LBhxaeq7s8Uzbc7efWXqfKfrmO5B8uLxXeKRgxegO4SFbcUQ0emPXpYW6C5lO19YwfLl\n DsQkd86rz0JmZemcQ/QBzY/06Mq7OilmTGEncalKDpWUZpN7fOEBpyAfOz2ZBoe3ssMs\n 8Oi1TraPLN39ZFaQYFFLUP7lPT8dJAg7j42JbsX8bIoOO2qUNfLFEZUg0J9+9LAxNYmn\n lvhg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774610284; x=1775215084;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=9Sc6A8mUH5H33CEhbJhf4m2nOob0B+CIV382Sacc+zU=;\n b=ct4BsuB8HYNcSTLB5ig/qxnnMwT3ojPX6rKZ7PSwtmmmUHfBxdyNtISLgXhho6QMz4\n otXFipIl1qIJpV5FBWPRaFVRYc2Cg2B1j0iDQjCtUsMQd8bBUq7k9ef/fUHX6xpsG+d1\n BgpSfu7LPVHcEh8tCb6AJqv/9PVlbUGThIuz2ug58N0iMOet5Wtw5/RYIxPN+TLYmv/z\n lMVgtugRkpwrKhz5HjY0sz2TxoR0//Hp+05W15MkzNQm6IjIzau7Vj7AvqXhGed6Wq53\n QtO1O6FqOK5cLQK23J5dXIgQidwrMzl1FO/E4tkP5OmOOyve6eeh7D+IrVdZDjT8ZOMf\n GS2w==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCVxw24k9Fu5HvCtArMG/ENEnzfhm2uvOLwiw5BsYcQPzxk2rSEtXKGMChOegPsPSPJg/AEm4AFoMris@nongnu.org", "X-Gm-Message-State": "AOJu0YyZuhenEX/dkWAKnnaWKjrARTFraXsGzvFlLxVq8jP+zj1Ow06x\n leaYnVrC4bovhN5bwZlFLZ6aNyr0Y/IVd1cgk9CbxHP/ZDMa3rfaX3Q0uIRJ2JPJz9s=", "X-Gm-Gg": "ATEYQzxTr3idkRZVgZyI2PQlMbFJ7+spf52KnyBHB7KauRan1MZh0GR6x+I7mBgI/ST\n Vvz4artLubh4VxmuNqk3cBM9SC/4DCIfVIBQCPUy2xkoaiN28kJ7ykjxsyYl5hxzDVdbfauXb3f\n WOSEpS9bZp7BqsslLQZ271B21irY+3R102kVPMSfRQ+w4nSvlZIAiRPztFad0Vs271EVrwJURH0\n LePsKymVLRN1VShFwkpBMsJUY13LJgGhuIcTquNm7KBOlBVGM10m1CrkZ+OrAjVFKA0GKQHifeL\n ZTcnqLr7AEhAckNgL9mMr571xhZ1tMcBAA9mVVL4laLuBEumiKceA/jMKWLWCubauXCJ6Mwr0qS\n PmqPG8+gJBkIKjfRvA5Er8rOiRQRw1/NJT/OFl3NsHfhirFS0oxyF2X8wrI8E2afWtUbwYUeY2A\n 9AigNwgvWYOYamDcmw3Mu859tgRfeac07poah733z5pjGDCPvBr/4YLycYHxBi0VEJPxvz9r4kB\n BcNhRSJu6vRkuj7nW5wk7Du8SDxkIHkfg9P31LsUQ==", "X-Received": "by 2002:a5d:5f42:0:b0:439:de1d:74ae with SMTP id\n ffacd0b85a97d-43b9e9fa204mr3373603f8f.22.1774610283900;\n Fri, 27 Mar 2026 04:18:03 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Jonathan Cameron <jonathan.cameron@huawei.com>", "Subject": "[PATCH v2 65/65] hw/arm/virt: Allow user to select GICv5", "Date": "Fri, 27 Mar 2026 11:17:00 +0000", "Message-ID": "<20260327111700.795099-66-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327111700.795099-1-peter.maydell@linaro.org>", "References": "<20260327111700.795099-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::431;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Allow the user to select a GICv5 via '-machine gic-version=x-5', and\ndocument this. The 'x-' prefix indicates that the emulation is still\nin an \"experimental\" state as far as QEMU is concerned; the\ndocumentation describes what \"experimental\" means for the user and\nwhat parts are not yet implemented.\n\nWe do not make 'gic-version=max' enable GICv5 here because:\n\n * the GICv5 architectural spec is still at the EAC level and could\n have minor changes between now and its final version; only users\n who specifically want to start working with the GICv5 should\n select it\n * QEMU's implementation here is still not fully featured, and\n selecting it instead of GICv3 will mean losing functionality such\n as MSIs\n * the GICv5 is not backwards compatible with the GICv3/GICv4 for\n system software, so silently \"upgrading\" an existing command line\n to GICv5 is just going to break existing guest kernels\n\nThe last one in particular suggests that even when the emulation\nmoves out of \"experimental\" status we will probably not want to\nchange \"max\".\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n docs/system/arm/virt.rst | 19 +++++++++++++++++++\n hw/arm/virt.c | 11 ++++++++---\n 2 files changed, 27 insertions(+), 3 deletions(-)", "diff": "diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst\nindex fbe3ca9e12..f811e662d6 100644\n--- a/docs/system/arm/virt.rst\n+++ b/docs/system/arm/virt.rst\n@@ -161,6 +161,25 @@ gic-version\n GICv3. This allows up to 512 CPUs.\n ``4``\n GICv4. Requires ``virtualization`` to be ``on``; allows up to 317 CPUs.\n+ ``x-5``\n+ GICv5 (experimental). This is an experimental emulation of the GICv5,\n+ based on the EAC release of the GICv5 architecture specification.\n+ Experimental means:\n+\n+ - guest-visible behaviour may change when the final version of\n+ the specification is released and QEMU implements it\n+ - migration support is not yet implemented\n+ - the GICv5 is not exposed to the guest via ACPI tables, only via DTB\n+ - the way the interrupt controller is exposed to the guest and the\n+ command line syntax for enabling it may change\n+\n+ The current implementation supports only an EL1 guest (no EL2 or\n+ EL3 and no Realm support), and does not implement the ITS (no\n+ MSI support).\n+\n+ Note that as the GICv5 is an Armv9 feature, enabling it will\n+ automatically disable support for AArch32 at all exception levels\n+ except for EL0 (userspace).\n ``host``\n Use the same GIC version the host provides, when using KVM\n ``max``\ndiff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex 0aff58bc3c..0064491063 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -3223,6 +3223,9 @@ static char *virt_get_gic_version(Object *obj, Error **errp)\n const char *val;\n \n switch (vms->gic_version) {\n+ case VIRT_GIC_VERSION_5:\n+ val = \"x-5\";\n+ break;\n case VIRT_GIC_VERSION_4:\n val = \"4\";\n break;\n@@ -3240,7 +3243,9 @@ static void virt_set_gic_version(Object *obj, const char *value, Error **errp)\n {\n VirtMachineState *vms = VIRT_MACHINE(obj);\n \n- if (!strcmp(value, \"4\")) {\n+ if (!strcmp(value, \"x-5\")) {\n+ vms->gic_version = VIRT_GIC_VERSION_5;\n+ } else if (!strcmp(value, \"4\")) {\n vms->gic_version = VIRT_GIC_VERSION_4;\n } else if (!strcmp(value, \"3\")) {\n vms->gic_version = VIRT_GIC_VERSION_3;\n@@ -3252,7 +3257,7 @@ static void virt_set_gic_version(Object *obj, const char *value, Error **errp)\n vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */\n } else {\n error_setg(errp, \"Invalid gic-version value\");\n- error_append_hint(errp, \"Valid values are 2, 3, 4, host, and max.\\n\");\n+ error_append_hint(errp, \"Valid values are 2, 3, 4, x-5, host, and max.\\n\");\n }\n }\n \n@@ -3827,7 +3832,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)\n virt_set_gic_version);\n object_class_property_set_description(oc, \"gic-version\",\n \"Set GIC version. \"\n- \"Valid values are 2, 3, 4, host and max\");\n+ \"Valid values are 2, 3, 4, x-5, host and max\");\n \n object_class_property_add_str(oc, \"iommu\", virt_get_iommu, virt_set_iommu);\n object_class_property_set_description(oc, \"iommu\",\n", "prefixes": [ "v2", "65/65" ] }