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GET /api/patches/2216905/?format=api
{ "id": 2216905, "url": "http://patchwork.ozlabs.org/api/patches/2216905/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-37-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-37-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:31", "name": "[v2,36/65] target/arm: GICv5 cpuif: Implement GICv5 PPI active set/clear registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e0bb180afeac91c08d1059e4ea64f36f77153da8", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-37-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216905/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216905/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=le5DwtnM;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhytG1gMkz1yGL\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:22:46 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65CG-00074Q-Ie; Fri, 27 Mar 2026 07:17:48 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C8-0006vh-UM\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:40 -0400", "from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65C6-0008Aw-AD\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:39 -0400", "by mail-wr1-x42f.google.com with SMTP id\n ffacd0b85a97d-439cd6b09f8so1307546f8f.3\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:37 -0700 (PDT)", "from lanath.. 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In both cases, reads\nreturn the current state.\n\nWe start here by implementing the accessors for the underlying state;\nwe don't yet attempt to do anything (e.g. recalculating the highest\npriority pending PPI) when the state changes. That will come in\nsubsequent commits.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/cpu.h | 5 +++++\n target/arm/tcg/gicv5-cpuif.c | 38 ++++++++++++++++++++++++++++++++++++\n 2 files changed, 43 insertions(+)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex a32c5f3ab1..dd4dc12feb 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -257,6 +257,9 @@ typedef enum ARMFPStatusFlavour {\n } ARMFPStatusFlavour;\n #define FPST_COUNT 10\n \n+/* Architecturally there are 128 PPIs in a GICv5 */\n+#define GICV5_NUM_PPIS 128\n+\n typedef struct CPUArchState {\n /* Regs for current mode. */\n uint32_t regs[16];\n@@ -600,6 +603,8 @@ typedef struct CPUArchState {\n struct {\n /* GICv5 CPU interface data */\n uint64_t icc_icsr_el1;\n+ /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register */\n+ uint64_t ppi_active[GICV5_NUM_PPIS / 64];\n } gicv5_cpuif;\n \n struct {\ndiff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex 497c09474b..6672cda37f 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -175,6 +175,20 @@ static void gic_cdhm_write(CPUARMState *env, const ARMCPRegInfo *ri,\n gicv5_set_handling(gic, id, hm, domain, type, virtual);\n }\n \n+static void gic_ppi_cactive_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ uint64_t old = raw_read(env, ri);\n+ raw_write(env, ri, old & ~value);\n+}\n+\n+static void gic_ppi_sactive_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ uint64_t old = raw_read(env, ri);\n+ raw_write(env, ri, old | value);\n+}\n+\n static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n /*\n * Barrier: wait until the effects of a cpuif system register\n@@ -254,6 +268,30 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n */\n .resetfn = arm_cp_reset_ignore,\n },\n+ { .name = \"ICC_PPI_CACTIVER0_EL1\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 0,\n+ .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,\n+ .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[0]),\n+ .writefn = gic_ppi_cactive_write,\n+ },\n+ { .name = \"ICC_PPI_CACTIVER1_EL1\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 1,\n+ .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,\n+ .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[1]),\n+ .writefn = gic_ppi_cactive_write,\n+ },\n+ { .name = \"ICC_PPI_SACTIVER0_EL1\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 2,\n+ .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[0]),\n+ .writefn = gic_ppi_sactive_write,\n+ },\n+ { .name = \"ICC_PPI_SACTIVER1_EL1\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 3,\n+ .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_active[1]),\n+ .writefn = gic_ppi_sactive_write,\n+ },\n };\n \n void define_gicv5_cpuif_regs(ARMCPU *cpu)\n", "prefixes": [ "v2", "36/65" ] }