Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2216935/?format=api
{ "id": 2216935, "url": "http://patchwork.ozlabs.org/api/patches/2216935/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-45-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-45-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:39", "name": "[v2,44/65] target/arm: GICv5 cpuif: Implement ICC_CR0_EL1", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "205d91b4e47a84a3c954a70064e7f7a6d6576ed3", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-45-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216935/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216935/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=xvA08mui;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyzM67NXz1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:27:11 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65CK-00077m-2q; Fri, 27 Mar 2026 07:17:52 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CG-000748-BJ\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:48 -0400", "from mail-wr1-x434.google.com ([2a00:1450:4864:20::434])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65CD-0008Lh-L0\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:47 -0400", "by mail-wr1-x434.google.com with SMTP id\n ffacd0b85a97d-439b97a8a8cso2030565f8f.1\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:45 -0700 (PDT)", "from lanath.. (wildly.archaic.org.uk. [81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.43\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 27 Mar 2026 04:17:43 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1774610264; x=1775215064; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=zvlMSNGdKIlUIEkOr6Lv47MQTuNcGu0po65x29YyYWY=;\n b=xvA08muiTPDIAglBq2VgMo9I+53CQBL9ClNG+yD0wi0AQw8U/ERkNTETYr/yZ/JSXP\n V2YetGN2p91aoOasnpvSUKa4hIUM0dQx//yrMDScvzfd+qRiX5c37WX67COfjZFXwg2C\n y1AILrI9auvrrEBv3P6V3TVJ7NvFRQIEm7fYhPT1X+e1k8MHEGPa0HzhEizcESCy/768\n u50bHlqiWFNdABfHP8rJ6FblFn8QrgNj26ov8JxHPURk+z8dzYAEqYmrisXo74d0bIUF\n PC64sbz5h/JoMfqMAw2tjkdtNmgoaEEu9hAVUWZi3vcHmJ8GQEtk8y8/rbGTcmWAJ2hB\n n++g==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774610264; x=1775215064;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=zvlMSNGdKIlUIEkOr6Lv47MQTuNcGu0po65x29YyYWY=;\n b=r+KkJWRruufYQQRrqZl/RPK0AMiVHirxjmGmP5s4AQsdu9yt7w+AkwV7nsxFlEt4va\n vn05JwPSjjDRX64NCGalDTgV3D5DSr/6lDNVPmyrUX0B2KFr3rQM4Pe22GSdlDhVpptk\n FpCQX0Kkk1vDitVLLtmE81M9dlgC7wvo9Bs5rZE26EP1gus/rnc+2hOzFf8LRx4dVLrH\n uJzejWNG3XPzH6XOk/QW50bTaMyKY9J2KlokgbaK++kGkUi2/V5CkOVjk4Ll5wvhv56u\n dP/ASWVLcVdeClxVl76+YE6WjVh89jiQHDGLFda++AlaAbJSgC3cr4ja/sKIQN/n9etu\n RKAw==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCUkl2A0qRxsrG3UWDmAGoETK99lslkvesJiwMEBxo9m8tzFMyyP09uNpqSb1oTWY0ZIyhW7qpYlrkGm@nongnu.org", "X-Gm-Message-State": "AOJu0YwhQxPBVEA2Ryhm1BHEdUHsgs/dn+/9fbH0X4pcz1UiYw1vuM0s\n wfN9HgJOyV2ZE0h/1aOnN/6FTCC3CzWaoIZQg4BTR16yNe4tR3frOqvivLfUw/h6zh6QlAYL1fC\n qfaA0P/s=", "X-Gm-Gg": "ATEYQzw8jZR0BLtHAsaKWF+nr+izQEPGpJ7Oe/rIiGBabfHDdLEdoQTh29xIBtaYAvK\n SDPNgssZMfJyUvRH6iu5xrnqxmKDTVAVPrGFalGUwtf0xuxnHYjx90gQVtR4RH75OvNQeAljzSp\n 94BAxTPpWrkMkTKUTHuvnoWnJPpZl2Rx8HGTw71xlj5itOA/UXlA95lxkbLjp/RWgnCTxNYAf8z\n EiqSfNn6NVACm8uEv0Q/DQDZToDuKEEY+DzSRRsQhrhAQlt0vGG1KdB5dYxwAc7c0O2B9e2c0PU\n PmmAnEgtxIaU/4lmwi3a/YbC5utJH/iuyYYN72Zmq/nltcE+rCFXC5jYqotZ5538/DfDDnoDQ5p\n 9c4y5H8nzAFAXGHkCpy8gbFNS/USUNQki65RgPdFlUGbNyWFNvgvXFiTBYqKcmLl667ozoc2M/u\n /eCQhlwAccBjlilITThShaXIzAKLabkFrpKnCwV2ESKg40nVGDHAX6qTFJqdy9kL8ySE9g4CdLU\n rREhapmX792q8fxYbqZ97JH80kAUDs=", "X-Received": "by 2002:a05:6000:1787:b0:439:c5cf:fc73 with SMTP id\n ffacd0b85a97d-43b9e9e8c64mr3413778f8f.12.1774610264039;\n Fri, 27 Mar 2026 04:17:44 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Jonathan Cameron <jonathan.cameron@huawei.com>", "Subject": "[PATCH v2 44/65] target/arm: GICv5 cpuif: Implement ICC_CR0_EL1", "Date": "Fri, 27 Mar 2026 11:16:39 +0000", "Message-ID": "<20260327111700.795099-45-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327111700.795099-1-peter.maydell@linaro.org>", "References": "<20260327111700.795099-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::434;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Implement ICC_CR0_EL1, which is the main control register. This is\nbanked between interrupt domains in the same way as ICC_APR_*.\n\nThe GICv5 spec assumes that typically there will need to be a\nhardware handshake between the CPU and the IRS, which is kicked off\nby guest software setting a LINK bit in this register to bring the\nlink between the two online. However it is permitted to have an\nimplementation where the link is permanently up. We take advantage\nof this, so our LINK and LINK_IDLE bits are read-only and always 1.\n\nThis means the only interesting bit in this register for us is the\nmain enable bit: when disabled for a domain, the cpuif considers that\nthere is never an available highest priority interrupt.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n target/arm/cpu.h | 1 +\n target/arm/tcg/gicv5-cpuif.c | 44 ++++++++++++++++++++++++++++++++++++\n 2 files changed, 45 insertions(+)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex e0a7d02386..1263841a1d 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -605,6 +605,7 @@ typedef struct CPUArchState {\n /* GICv5 CPU interface data */\n uint64_t icc_icsr_el1;\n uint64_t icc_apr[NUM_GICV5_DOMAINS];\n+ uint64_t icc_cr0[NUM_GICV5_DOMAINS];\n /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register */\n uint64_t ppi_active[GICV5_NUM_PPIS / 64];\n uint64_t ppi_hm[GICV5_NUM_PPIS / 64];\ndiff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c\nindex ed7c30c07c..50aa81d74f 100644\n--- a/target/arm/tcg/gicv5-cpuif.c\n+++ b/target/arm/tcg/gicv5-cpuif.c\n@@ -43,6 +43,12 @@ FIELD(ICC_IDR0_EL1, ID_BITS, 0, 4)\n FIELD(ICC_IDR0_EL1, PRI_BITS, 4, 4)\n FIELD(ICC_IDR0_EL1, GCIE_LEGACY, 8, 4)\n \n+FIELD(ICC_CR0, EN, 0, 1)\n+FIELD(ICC_CR0, LINK, 1, 1)\n+FIELD(ICC_CR0, LINK_IDLE, 2, 1)\n+FIELD(ICC_CR0, IPPT, 32, 6)\n+FIELD(ICC_CR0, PID, 38, 1)\n+\n /*\n * We implement 24 bits of interrupt ID, the mandated 5 bits of priority,\n * and no legacy GICv3.3 vcpu interface (yet)\n@@ -346,6 +352,37 @@ static uint64_t gic_icc_hapr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)\n return gic_running_prio(env, gicv5_current_phys_domain(env));\n }\n \n+/* ICC_CR0_EL1 is also banked */\n+static uint64_t gic_icc_cr0_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)\n+{\n+ GICv5Domain domain = gicv5_logical_domain(env);\n+ return env->gicv5_cpuif.icc_cr0[domain];\n+}\n+\n+static void gic_icc_cr0_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ /*\n+ * For our implementation the link to the IRI is always connected,\n+ * so LINK and LINK_IDLE are always 1. Without EL3, PID and IPPT\n+ * are RAZ/WI, so the only writeable bit is the main enable bit EN.\n+ */\n+ GICv5Domain domain = gicv5_logical_domain(env);\n+ value &= R_ICC_CR0_EN_MASK;\n+ value |= R_ICC_CR0_LINK_MASK | R_ICC_CR0_LINK_IDLE_MASK;\n+\n+ env->gicv5_cpuif.icc_cr0[domain] = value;\n+}\n+\n+static void gic_icc_cr0_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri)\n+{\n+ /* The link is always connected so we reset with LINK and LINK_IDLE set */\n+ for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.icc_cr0); i++) {\n+ env->gicv5_cpuif.icc_cr0[i] =\n+ R_ICC_CR0_LINK_MASK | R_ICC_CR0_LINK_IDLE_MASK;\n+ }\n+}\n+\n static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n /*\n * Barrier: wait until the effects of a cpuif system register\n@@ -504,6 +541,13 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {\n .writefn = gic_icc_apr_el1_write,\n .resetfn = gic_icc_apr_el1_reset,\n },\n+ { .name = \"ICC_CR0_EL1\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 1,\n+ .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n+ .readfn = gic_icc_cr0_el1_read,\n+ .writefn = gic_icc_cr0_el1_write,\n+ .resetfn = gic_icc_cr0_el1_reset,\n+ },\n { .name = \"ICC_HAPR_EL1\", .state = ARM_CP_STATE_AA64,\n .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 3,\n .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW,\n", "prefixes": [ "v2", "44/65" ] }