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GET /api/patches/2216924/?format=api
{ "id": 2216924, "url": "http://patchwork.ozlabs.org/api/patches/2216924/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-9-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327111700.795099-9-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-27T11:16:03", "name": "[v2,08/65] hw/intc/arm_gicv5: Create inbound GPIO lines for SPIs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ad6210f804c7ccc9fc97034db660ffc299fd603c", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327111700.795099-9-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497750, "url": "http://patchwork.ozlabs.org/api/series/497750/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497750", "date": "2026-03-27T11:16:25", "name": "arm: Implement an emulation of GICv5 interrupt controller", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497750/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216924/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216924/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=n/TanvUf;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyx673zhz1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:25:14 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65Br-0006WT-Lh; Fri, 27 Mar 2026 07:17:23 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Bh-0006Nt-Bi\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:13 -0400", "from mail-wr1-x435.google.com ([2a00:1450:4864:20::435])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w65Be-0007jf-VC\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:17:12 -0400", "by mail-wr1-x435.google.com with SMTP id\n ffacd0b85a97d-439fe4985efso1507221f8f.3\n for <qemu-devel@nongnu.org>; Fri, 27 Mar 2026 04:17:10 -0700 (PDT)", "from lanath.. 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[81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43b919cf2b2sm15484227f8f.18.2026.03.27.04.17.08\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 27 Mar 2026 04:17:08 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1774610229; x=1775215029; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=ZSYEcEWU8r5tbbT6wFppapn1QdgzR56tHNGZiMLYIEE=;\n b=n/TanvUfvJuYl4bXGG9Gm+67dn/ukX5VuO0DXogeN2JWgICnjnFRx7Ax/jH8rWKNk8\n QjU9rPAnZV29fzFwcqOsS1DRDTcIVsq7jOnW3ar350LP1JDWyFTTyJvdNzv9o+yKkhxh\n 5+oG4qFEXhziYvR0pc2F6Lk+QOn6Y9oD4TXYLqxxJF13SFfvYj+E0vf6YwVxjFseIds9\n mZorseGYj88ZD0fwz0QtYlG1C+YiQ2PcDvRX7qGHzLw6z7a1ZeYtdIZXv2x5+N2RxXcj\n c/0Z5s7sWB3xg3z90KWI04s1e0jlB8nElP0fM/nTr7eeALCsvqNsXWMf5NbSISxCuSWT\n Aa2w==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774610229; x=1775215029;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=ZSYEcEWU8r5tbbT6wFppapn1QdgzR56tHNGZiMLYIEE=;\n b=q2a/+aZvzJbfU830T8g6XbbA0KC3CUQujzzN9JQmFbGBetb7CjzqF8KgxxajeXLrUY\n Mc1KqIyBmMJcU1qGAnVW9km52SisGJUdg1kV/pAn3h4aoGDP9hqFmkvEP5Tl5ntJhu8/\n PMqMISBHc6GSDMk7hRstT4fl2L5WefTznUCZ6d1FdDLtjsgopB6XaZdQ9KtVAkgp2kYj\n QETu/D5V/eoP4tIK4oC3USPQaDOu5GV8hc+x7gY30AMAWSo/KPd/lsyzHTHIzW79rqUa\n bhABpihtOHVDRH9RjWR2/y4068voTC/9E8oE4rC0qY+Oy94Db10yXiF7eLveRGNdjF3o\n bwxQ==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCWzzMy8y+FJv26lbqQ7JpddgUtR4kv6HSLDOJSJUcsvCKaYikmVtmxhYawriqMN9vZj5stoMbkrMLeu@nongnu.org", "X-Gm-Message-State": "AOJu0Yxj2+nZ3M7+vCkMJ+IToPQT9b2XeWXcPBarNmEHENd3VGE7Stx7\n XaJP2EUqZ13KvDSf6pQdZhS+tiCP+g3HSbDRvYA6Dfdl6y3B+Oi7iQX0/AdpHYnkcQo=", "X-Gm-Gg": "ATEYQzxpvC3N+sfnG8V96CzayTnA5cBMLSlGsi42ovKdWez/R8O+WSGZLkFO/Vcc15k\n b7BiTA2W+xzr/aDj/YFZux7iSYa91ABzTTc4lXNY1vxlSndaagKF5QiABHT37TBGtLiJuWNAfc+\n ddXxMuKhDUCWr45zJVC3gU8lnTtaxkwYo0drkigwMAq7UtvjdFQ2xx+lQ5QKA1/qPNGkYsFcuvP\n U4t47O9b7D3EfE3WRqJVsJ8mVhUauHNJPxUrBt4+PmgA42xYxsa2h5h2WmPR33XqeXQo9Jup9Go\n v8MtjATG0YrjWCtoHR0SVvXyvQ3WohIqhV4475cV7mQG+Dw/icIRSAmKpNyq3L67R2aZHc3X3DD\n yu3RqLogZ2YF//seFZYpKoP1ySYFK8upC0/0xy3lmI7M3HrO9NDkAPtYH0oHiOBDkxHNEgdYGVo\n zs4M1mOdd3jRJ8z63R0Dzt89wtutXRwDjqYDmXxzd67D9GUoFHzg2OGNHE7CAXAZKC1as5LLqAF\n HD5hBjvhSM7bsqFCRFhMB3zalnCBrY=", "X-Received": "by 2002:a5d:64c5:0:b0:43b:5356:a7fb with SMTP id\n ffacd0b85a97d-43b9ea775e8mr3015595f8f.49.1774610229392;\n Fri, 27 Mar 2026 04:17:09 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Jonathan Cameron <jonathan.cameron@huawei.com>", "Subject": "[PATCH v2 08/65] hw/intc/arm_gicv5: Create inbound GPIO lines for\n SPIs", "Date": "Fri, 27 Mar 2026 11:16:03 +0000", "Message-ID": "<20260327111700.795099-9-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327111700.795099-1-peter.maydell@linaro.org>", "References": "<20260327111700.795099-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::435;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The GICv5 IRS may have inbound GPIO lines corresponding to SPIs\n(shared peripheral interrupts). Unlike the GICv3, it does not deal\nwith PPIs (private peripheral interrupts, i.e. per-CPU interrupts):\nin a GICv5 system those are handled entirely within the CPU\ninterface. The inbound GPIO array is therefore a simple sequence of\none GPIO per SPI that this IRS handles.\n\nCreate the GPIO input array in gicv5_common_init_irqs_and_mmio().\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n hw/intc/arm_gicv5.c | 11 ++++++++++-\n hw/intc/arm_gicv5_common.c | 5 +++++\n hw/intc/trace-events | 1 +\n include/hw/intc/arm_gicv5_common.h | 4 ++++\n 4 files changed, 20 insertions(+), 1 deletion(-)", "diff": "diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c\nindex 64bec16bdd..cb1234b022 100644\n--- a/hw/intc/arm_gicv5.c\n+++ b/hw/intc/arm_gicv5.c\n@@ -160,6 +160,15 @@ static const MemoryRegionOps config_frame_ops[NUM_GICV5_DOMAINS] = {\n FRAME_OP_ENTRY(el3, GICV5_ID_EL3),\n };\n \n+static void gicv5_set_spi(void *opaque, int irq, int level)\n+{\n+ /* These irqs are all SPIs; the INTID is irq + s->spi_base */\n+ GICv5Common *cs = ARM_GICV5_COMMON(opaque);\n+ uint32_t spi_id = irq + cs->spi_base;\n+\n+ trace_gicv5_spi(spi_id, level);\n+}\n+\n static void gicv5_reset_hold(Object *obj, ResetType type)\n {\n GICv5 *s = ARM_GICV5(obj);\n@@ -196,7 +205,7 @@ static void gicv5_realize(DeviceState *dev, Error **errp)\n * NS domain.\n */\n cs->implemented_domains = (1 << GICV5_ID_NS);\n- gicv5_common_init_irqs_and_mmio(cs, config_frame_ops);\n+ gicv5_common_init_irqs_and_mmio(cs, gicv5_set_spi, config_frame_ops);\n }\n \n static void gicv5_init(Object *obj)\ndiff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c\nindex 3448734686..b58913b970 100644\n--- a/hw/intc/arm_gicv5_common.c\n+++ b/hw/intc/arm_gicv5_common.c\n@@ -38,10 +38,15 @@ static const MemoryRegionOps bad_frame_ops = {\n };\n \n void gicv5_common_init_irqs_and_mmio(GICv5Common *cs,\n+ qemu_irq_handler handler,\n const MemoryRegionOps config_ops[NUM_GICV5_DOMAINS])\n {\n SysBusDevice *sbd = SYS_BUS_DEVICE(cs);\n \n+ if (cs->spi_irs_range) {\n+ qdev_init_gpio_in(DEVICE(cs), handler, cs->spi_irs_range);\n+ }\n+\n for (int i = 0; i < NUM_GICV5_DOMAINS; i++) {\n g_autofree char *memname = g_strdup_printf(\"gicv5-irs-%d\", i);\n const MemoryRegionOps *ops = gicv5_domain_implemented(cs, i) ?\ndiff --git a/hw/intc/trace-events b/hw/intc/trace-events\nindex 54777f6da3..0797a23c1a 100644\n--- a/hw/intc/trace-events\n+++ b/hw/intc/trace-events\n@@ -232,6 +232,7 @@ gicv5_read(const char *domain, uint64_t offset, uint64_t data, unsigned size) \"G\n gicv5_badread(const char *domain, uint64_t offset, unsigned size) \"GICv5 IRS %s config frame read: offset 0x%\" PRIx64 \" size %u: error\"\n gicv5_write(const char *domain, uint64_t offset, uint64_t data, unsigned size) \"GICv5 IRS %s config frame write: offset 0x%\" PRIx64 \" data 0x%\" PRIx64 \" size %u\"\n gicv5_badwrite(const char *domain, uint64_t offset, uint64_t data, unsigned size) \"GICv5 IRS %s config frame write: offset 0x%\" PRIx64 \" data 0x%\" PRIx64 \" size %u: error\"\n+gicv5_spi(uint32_t id, int level) \"GICv5 SPI ID %u asserted at level %d\"\n \n # arm_gicv5_common.c\n gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base, uint32_t spi_irs_range, uint32_t spi_range) \"GICv5 IRS realized: IRS ID %u, %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u\"\ndiff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5_common.h\nindex ea01b2a1db..10276d652f 100644\n--- a/include/hw/intc/arm_gicv5_common.h\n+++ b/include/hw/intc/arm_gicv5_common.h\n@@ -29,6 +29,9 @@\n * IRS (this is IRS_IDR7.SPI_BASE); default is 0\n * + QOM property \"spi-irs-range\": number of SPI INTID.ID managed on this\n * IRS (this is IRS_IDR6.SPI_IRS_RANGE); defaults to value of spi-range\n+ * + unnamed GPIO inputs: the SPIs handled by this IRS\n+ * (so GPIO input 0 is the SPI with INTID SPI_BASE, input 1 is\n+ * SPI_BASE + 1, and so on up to SPI_BASE + SPI_IRS_RANGE - 1)\n *\n * sysbus MMIO regions (in order matching IRS_IDR0.INT_DOM encoding):\n * - IRS config frame for the Secure Interrupt Domain\n@@ -91,6 +94,7 @@ struct GICv5CommonClass {\n * of MemoryRegionOps structs.\n */\n void gicv5_common_init_irqs_and_mmio(GICv5Common *cs,\n+ qemu_irq_handler handler,\n const MemoryRegionOps ops[NUM_GICV5_DOMAINS]);\n \n /**\n", "prefixes": [ "v2", "08/65" ] }